CSE 140L Discussion 3

1
CSE 140L Discussion 3

• CK Cheng and Thomas Weng
• 4-bit adder, multiplexer, timing diagrams,
  propagation delays

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Timing behavior

• Real circuits have delays
• Gate delay time it takes for an output of the
  gate to change after its input changes
• We can simulate timing delays in Quartus II to
  see these delays

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Gate delay

• Notice rise time, fall time, and gate delay

input
output
input
output
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Quartus II Timing Simulation
Notice the delay in the output
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4-bit Ripple Carry Adders

• 4-bit ripple carry adder
• Chain 4 1-bit full adders together, and connect
  the carry out of the previous adder with the
  carry in of the next adder.
• Delay path critical path from A0, B0, or C0 to
  S3, C4

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Critical Path for worst delay

• Propagation from C0 to C4
• C4 changes as C0 toggles

C0
1110 0001
C4
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Multiplexers
-Multiplexers (MUXes) are like selectors. There
is one output, 2 or more inputs, and a selector
input that determines which of those inputs gets
outputed. -Allows several devices to share one
single line.
This is a 21 mux. It has 2 inputs, 1 output.
Because there are only 2 inputs, S is one bit. If
S0, then we output A. If S1, then we output B.
A
MUX
Z
B
S
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Multiplexers
-Here is the truth table for the 1-bit 21 MUX.
When S is 0, the MUX will select whatever A is.
If A is 1, then the MUX will output 1. It doesnt
matter what B is. When S is 1, then the MUX will
output whatever B is.
The boolean equation can be written as Z (A
S) (B S)
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Multiplexers
-MUX can be implemented very simply. -The two AND
gates determine which of the two inputs goes
through. If S is 0, then I0 will be ANDed with a
1, so that goes through. I1 will be ANDed with a
0, and thus wont go through.
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Multiplexers
-We can also make a 41 MUX using three 21 MUX
If S1S0 00, then S1 will select MUX from A and
B. Since S00. Z A.
A
0
MUX
1
B
0
Z
MUX
S0
Z
1
C
0
MUX
S1
D
1
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Multiplexers
-We can make 41 and above MUXes too. -With 4
inputs, our selector needs to have two bits.