Functions, Procedures

1
Lecture 10

• Functions, Procedures Packages

Read Chapter 7 and 8
(Part of the slides are from VHDL Design
Representation and Synthesis and Prof. Chathas
slides in ASU)
2
Procedures and Functions

• VHDL provides two sub-program constructs
• Procedure generalization for a set of
• statements.
• Function generalization for an expression.
• Both procedure and function have an interface
• specification and body specification.

3
Declaration of Procedures and Functions

• Both procedure and functions can be declared
• in the declarative parts of

• Process

• Entity

• Architecture

• Package interface

• Other procedures and functions

4
Function

• Function is a generalization of a expression
• a b c - d
• a f1(b,c,d)
• Hence, a function always returns a value.

subprogram_body lt pure impure
function id ( parameter_interface_list )
return type_mark is subprogram declarative
part begin sequential statement end
procedure id
5
Example 1

• Declaration
• function XYZ(M INTEGER) return INTEGER is
• variable N INTEGER
• begin
• -------------------
• -------------------
• N --------- some expression
• return N
• end XYZ

6
Primary Uses of Functions

• Operator implementation
• Type conversion
• Resolution Function

7
Wired AND Resolution Function
type TS is (0, 1, Z) type TSV is (NATURAL
range ltgt) of TS function WIRED_AND(S TSV)
return TS is variable RESOLVED_VALUE
Z begin for I in Srange loop if S(I)
0 then RESOLVED_VALUE 0
exit elsif S(I) 1 then
RESOLVED_VALUE 1 end if end
loop return RESOLVED_VALUE end WIRED_AND
8
Edge Detection Function
USE STD.std_logic.ALL -- define wlogic, 4
values, (x,0,1,z) ENTITY dff IS PORT(d, clk
IN t_wlogic q OUT t_wlogic) FUNCTION
rising_edge (SIGNAL S t_wlogic)
RETURN BOOLEAN IS BEGIN IF (SEVENT)
AND (S 1) AND (SLAST_VALUE
0) THEN -- why ? RETURN TRUE
ELSE RETURN FALSE - END IF
END rising_edge END dff
1
1
9
Use of Function

• architecture BEHAVE of dff is
• BEGIN
• PROCESS(clk)
• BEGIN
• IF rising_edge(clk) THEN
• q lt d
• END IF
• END PROCESS
• END BEHAVE

10
Recursive Functions

• Functions that call themselves
• Example Fibonacci Series
• Fo 1, F1 1, Fi Fi-1 Fi-2 igt2

N 0 1 2 3 4 5 6 7 -- F 1 1
2 3 5 8 13 21 --
11
Function Implementation

• function FIBO(N NATURAL) return POSITIVE is
• begin
• if N 0 or N 1 then
• return 1
• else
• return FIBO(N -1) FIBO(N - 2)
• end if
• end FIBO

FIBO(2) FIBO(1)FIBO(0) 2 1
1
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Scope of declarations
architecture arch of ent is type t is . signal
s t procedure p1 () is variable v1 t begin v1
s end procedure begin proc1 process
is variable v2 t procedure p2 () is variable
v3t begin end procedure
begin p1 p2(v2) end process proc2 process
is begin p1() end process end architecture
v1
t, s, p1
v2, p2
v3
13
Functions pure and impure

• A pure function is one that does not refer to
  any
• variables or signals outside its body.

architecture arch of ent is type t is . signal
s t impure function p1 () return bit
is variable v1 t begin v1 s .. end
function begin
Functions are pure by default.

• An impure function is one that refers to
  variables
• and signals outside the function body.

14
Overloading

• Overloading refers to using the same procedure
• (or function) name to define two or more
  procedures
• that operate on different types or number
• of parameters.

procedure incr (a in integer n in
integer) procedure incr (a in bit_vector n in
integer) procedure incr (a in integer)

• VHDL also permits overloading of operator
  symbols
• like , -, and so on.

15
Overloading example
function (left,right bit_vector) return
bit_vector is begin end function
variable a, b, c bit_vector(7 downto 0) c a
b
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Procedure
subprogram_body lt procedure id (
parameter_interface_list ) is subprogram
declarative part begin sequential statement
end procedure id
17
Example
procedure ONES_AND_ZEROS_CNT (variable X in
BIT_VECTOR(0 to 2) variable N_ONES, N_ZEROS
out BIT_VECTOR(0 to 1)) is variable NUM1
INTEGER range 0 to 3 0 variable NUM0
INTEGER range 0 to 3 0 begin for I in 0
to 2 loop if X(I) 1 then NUM1
NUM1 1 else NUM0 NUM0
1 end if end loop
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Example Continued
case NUM1 is when 0 gt N_ONES 00
when 1 gt N_ONES 01 when 2 gt
N_ONES 10 when 3 gt N_ONES 11
end case case NUM0 is when 0 gt
N_ZEROS 00 when 1 gt N_ZEROS 01
when 2 gt N_ZEROS 10 when 3 gt
N_ZEROS 11 end case end procedure
ONES_AND_ZEROS_CNT
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Use of Procedure
Architecture NOTHING of SOMETHING
is begin process(INP) variable N1, N0
BIT_VECTOR(0 to 1) variable Z
BIT_VECTOR(0 to 2) begin Z INP
ONES_AND_ZEROS_CNT(Z, N1, N0) OUT1 lt
N1 OUT0 lt N0 end process end
architecture NOTHING
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Representing a Full AdderWith a Function
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Procedure To Add Bit Vectors
procedure ADD(A,B in BIT_VECTOR CIN in BIT
SUM out BIT_VECTOR COUT out BIT)
is variable SUMV,AV,BV BIT_VECTOR(A'LENGTH-1
downto 0) variable CARRY BIT begin AV
A BV B CARRY CIN for I in 0 to
SUMV'HIGH loop SUMV(I) AV(I) xor BV(I) xor
CARRY CARRY (AV(I) and BV(I)) or (AV(I)
and CARRY) or (BV(i) and CARRY)
end loop COUT CARRY SUM SUMV end
procedure ADD
22
Return statement

• A procedure executes till the end statement,
  OR
• It encounters a return statement.
• In either case, the control is transferred
  back to
• the calling process or subprogram.

return_stmt lt return
23
Return example
procedure mult_and is begin res 0 for
index in some_bit_vectorrange loop if
some_bit_vectorindex 0 then return end
if end loop res 1 end procedure
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Subprograms Allowable Modes and Objects For
Parameters
Procedure 1. Modes in, inout, and out. 2.
Object class constant, variable, and signals. 3.
If mode is in and no object class is specified,
constant is assumed. 4. If mode is inout or out
and no object class is specified variable is
assumed.
25
Subprograms Allowable Modes and Objects For
Parameters

• Function
• 1. Mode in only.
• 2. Object class must be constant or signal if
  none specified, constant is assumed.
• Call(for both)
• formals actuals
• signal signal
• variable variable
• constant expression

26
Example
Declaration function MAJ3(X BIT_VECTOR(0 to
2)) return BIT is begin return (X(0) and
X(1) or (X(0) and X(2)) or (X(1) and
X(2)) end MAJ3 Use C(1) lt MAJ3(A)
X is a constant, thus,A can be constant,
variable , or signal
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Packages

• Used to collect frequently used types, constants,
  signals, functions and procedures
• Can be globally accessed
• Labor saving
• Can be used to set up a modeling environment for
  an engineering group.

28
Example Package Declaration

• package HANDY is
• subtype BITVECT3 is BIT_VECTOR(0 to 2)
• subtype BITVECT2 is BIT_VECTOR(0 to 1)
• function MAJ3(X BIT_VECTOR(0 to 2))
• return BIT
• --------------------------- Other
• --------------------------- Declarations
• ---------------------------
• end package HANDY

29
Example Package Body

• package body HANDY is
• function MAJ3(X BIT_VECTOR(0 to 2))
• return BIT is
• begin
• return (X(0) and X(1)) or (X(0) and X(2))
• or (X(1) and X(2))
• end MAJ3
• --------------------------- Other Subprogram
• --------------------------- Definitions
• ---------------------------
• end package body HANDY

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Example Package Use

• use WORK.HANDY.ALL
• entity LOGSYS is
• port(X in BITVECT3 Y out BITVECT2)
• end entity LOGSYS

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Predefined package standard

• VHDL includes declarations of predefined types
  and
• operators that are stored in the library
  std.
• A user is not required to explicitly declare the
• standard library.
• The following declaration is implicit for each
  VHDL
• model file.

library std, work use std.standard.all
NOTE It does not include use work.all
32
Important Packages
Package STANDARD (LRM) --- no use clause
required TYPES SUBTYPES FUNCTIONS BOOLEAN POS
ITIVE NOW BIT NATURAL BIT_VECTOR CHARACTER SEV
ERITY_LEVEL INTEGER REAL TIME PACKAGE TEXTIO
(LRM) Contains types, function and procedures
for text I/O.
33
Important Packages
PACKAGE SYSTEM_4 (text CD) Contains types,
functions and procedures for MVL4 logic
system. IEEE Packages Type declarations,
functions, and procedures for IEEE Std.1164 (9
valued logic system) Synopsys Packages Provide
common types, functions, procedures and component
models for simulation users.
34
VHDL synthesis packages

• numeric_bit and numeric_std
• Both of them define arithmetic operations on
• integers represented using vectors of bit and
• std_logic elements.
• Both of them contain two basic types signed
• and unsigned

type unsigned is array (natural range ltgt) of
bit type signed is array (natural range ltgt) of
bit
35
VHDL mathematical packages

• Real number mathematical package and
• complex number mathematical package.
• Real number package defines various constants
• and functions.
• Complex number package defines complex numbers
• and functions that operate on complex numbers.