UK Electronics Status and Issues

1
UK Electronics Status and Issues

• Paul Dauncey
• Imperial College London

2
UK approval

• UK electronics project (finally!) approved in Dec
  2002
• Full equipment request, but only for ECAL
  electronics
• Full manpower request for engineering effort from
  Rutherford Laboratory (RAL)
• New engineer (Adam Baird, RAL) has now joined the
  project
• RAL will also do layout and some testing
• Budgeted to use all money and effort by the end
  of Mar 2004
• RAL people have experience of CMS tracker
• Significant knowledge of design of Front End
  Driver (FED)
• Readout board for CMS silicon tracker
• Architecture close to proposed CALICE board
• Will now use FED as a starting point for
  CALICE

3
CMS Tracker FED
5V
3.3V
Run/Halt
Config E2PROM
Id E2 Prom
1.5V
5V
3.3V
1.5V
1
0V
3.3V
Compact Flash
1
Test Connector
1
VME
LEDs
4x Prog Delay
1
Dual ADC
12x Opto Rx
1
Power Good
VME64x Interface FPGA
FPGA
Synch Processing
Boundary Scan
System ACE
Buffer Jumper Matrix
-5V
ASIC
12x trim dac
Vref
VME
FE 1
PD Array
3
6
4x Prog Delay
12V
12
Dual ADC
LEDs
Temp Sense
5V
Front End FPGA
3.3V
FPGA
Temp Sense
Clock Control Data
2.5V
1.5V
2.5V
0V
LEDs
2
1.5V
QDR SSRAM
-5.0V
spare
Over temp
LEDs
TTS
TTCrx
TTC
DAQ
Readout Synch Control
ASIC
FLT
LEDs
EMU
FSYNC
Spare
Process
Back End FPGA
LEDs
Transfer
VME
Temp Sense
43
85
22
Readout
Clock Control Data
4x Prog Delay
3.3V
1.5V
Dual ADC
8
Busy
12x Opto Rx
8
LEDs
error
FPGA
halted
Synch Processing
ASIC
12x trim dac
Vref
FE 8
PD Array
24
4x Prog Delay
48
5.0 V
96
E-Fuse Hot swap DC-DC
3.3 V
Front End FPGA
Dual ADC
FPGA
2.5V
Temp Sense
1.5V
-5.0V
extract
Hot swap cycle
SW
Live extract request
SW
4
FED layout

• Ideally, keep everything to the right, redo
  everything to the left
• Restricts readout board to same I/O and
  inter-FPGA paths as FED
• No major problems seen so far

5
Implications of using FED

• FED more complicated and hence expensive than
  previous design
• Keep cost within budget by increasing number of
  cables per board
• Previous design had 6 cables ( 6 VFE-PCBs) per
  board, new design has 16
• Total number of boards for the ECAL drops from 15
  to 6
• Cost per board should be around 6k 10k?
• Save on much of layout and some firmware design
• VME FPGA should be very close (if not identical)
  would like VME interrupts but not (yet)
  implemented
• Back end (BE) FPGA can reuse major parts of FED
  firmware
• Front end (FE) FPGA will need all new firmware
• BE FPGA much larger than needed
• Use spare logic for trigger handling no need for
  separate board
• Trigger I/O and distribution via J0/J2 backplane
  unused pins
• Requires adding termination resistors for
  incoming LVDS, i.e. changing layout of back of
  board

6
Implications of using FED (cont)

• Space for cable connectors, line
  drivers/receivers, ADCs, etc. restricted by
  position of FE FPGA
• Need to minimise the number of components here
• BE has 2?1MByte memories for event buffering
• With 16 cables, board event size 16?6?18?2
  3.5kBytes/event
• 2MBytes stores only around 500 events in each
  beam burst
• May need larger memories for CALICE i.e. would
  require changing layout of back of board
• 9U front panel so can fit 16 high-density 68-pin
  SCSI connectors
• 38 pins needed leaves 30 pins 15 differential
  lines spare
• Connected directly to FE FPGA for use as LVDS
• Could use as I/O lines for digital HCAL readout
• For more details, see
• http//www.hep.ph.ic.ac.uk/calice/electronics
  /electronics.html

7
ECAL assumed electronics schedule
2003 2004
8
Issues CALICE schedule and plans

• ECAL prototype test schedule
• When and where will prototype tests be done?
• ECAL final system schedule
• When and where is full readout electronics system
  needed?
• What sets this date and how firm is it?
• Will first use be beam, cosmics, calibration
  tests?
• HCAL schedule
• When will analogue and digital options be ready?
• Will either or both options use UK readout?
• Is a prototype test needed for the analogue?
• When and where will prototype test be done for
  digital?

9
Issues VFE-PCB interface

• Voltage levels still have some uncertainties
• Main problem would be negatively-shifted LVDS
• Needed for schematics before end February
• Confirm connector choice
• Compatibility with cable and connector needed at
  VFE-PCB
• Needed for schematics before end February
• Pin allocations within connector
• In principle, needed for schematics before end
  February
• If desperate, could wire cables to swap pins
  later before end May
• Cable specification
• Some cables required for VFE-PCB tests
• Need to be manufactured before end May
• Prototype board testing with semi-final VFE-PCB
• Needed before redesign before end November

10
Issues beam test details

• Laboratory requirements cable safety
  specification, etc.
• Needed for cable manufacture before end May
• Define number of events needed per beam spill
• Affects size of onboard memory required
• Also needs event size estimate per board from
  HCAL if using UK boards
• Needed for schematics before end February
• Cable lengths
• Distance between VME crate and ECAL/HCAL
• Needed for cable manufacture before end May
• Trigger logic and distribution
• Allocation of I/O lines with termination
  resistors
• Needed for assembly before end May
• Number of pins to be allocated on backplane for
  trigger fanout
• Needed for firmware design before end May

11
Issues HCAL plans

• Analogue is VFE-PCB interface compatible?
• For signal levels, cables, connectors
• Needed for schematics before end February
• Number of boards required for manufacture
  before end February 2004
• Digital interface specification
• Sufficient number of spare connector pins?
• Needed for schematics before end February
• Digital allocations of pins
• Have to mount termination resistors on correct
  lines
• Needed for assembly before end April
• Digital firmware development for spare pins
• UK unlikely to have manpower required
• Needed for digital HCAL tests before end
  November