ClockDelayed CD Domino Logic With Programmable Delay Elements PDE

1
Clock-Delayed (CD) Domino Logic With Programmable
Delay Elements (PDE)

• Miodrag Vujkovic, Gin Yee, and Carl Sechen
• VLSI Design and CAD Laboratory
• Department of Electrical Engineering
• University of Washington

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Non-inverting Gates

• Add transistor in parallel for OR - M circuits
  and enable transistor to disable branch in normal
  mode (enab 0)
• Add the longest branch in parallel for AOI
  circuits
• All logical inputs at 0 (outputs
  from the previous level
  
  (i-1) in precharge)
• clk(i) tied to transistor(s)
  in additional
  branch
• transistor sizes chosen
  to give worst-case
  delay
  from clk(i) to out

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Inverting Gates

• No need to add additional transistors
• All logical inputs at 0 (outputs from the
  previous level (i-1) in precharge)
• Size (speed) of the
  NAND gate is tuned
  
  to the speed of the
  nMOS dynamic gate
• Worst-case delay
  from clk(i) to out

4
Dual Gates

• Add transistor in parallel for and enable
  transistor to disable branch in normal mode (enab
  0)
• both outputs (inverting and non-inverting) should
  be scanned in separate cycles
• for inverting outputs
  
  enab 0
• for non-inverting
  outputs
  enab 1
• All logical inputs
  at 0 (outputs
  from the
  previous level (i-1)
  
  in precharge)

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Programmable Delay Element (PDE)

• PDE consists of two stages
• - 6 conditional inverters in parallel
• - strong output driver
• PDE delay is determined by the input combination
  bit5..0
• conditional inverters are geometrically sized
  w(n) 2w(n-1) 2nw0
• output inverter can be sized according to the
  load at i1 level

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General Clocking Scheme
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General Clocking Scheme (contd)
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Tuning process

• the circuits are fully levelized
• additional circuitry for each gate level-
  programmable delay element
• - 6-bit counter
• - error circuit
• - clock enable gate clock tree
• - 1 stage of the counter enable controller
• delay elements are tuned level by level
• while level i is being tuned, levels 1 to i-1 are
  in precharge phase (therefore level i inputs are
  at 0)
• only clk(i) and clk(i1) are enabled

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Error Circuit

• pMOS dynamic circuit (NAND) is used instead of
  nMOS
• clock is taken from the input of the final
  clock-tree stage of the level i1
• inputs to the pMOS transistors are the outputs
  from gates at the level i
• pMOS transistors
  can be small
  enough
• error err(i) is latched
  and used by Counter
  
  Enable Controller
• margin can be varied by
  shifting clk(i1)
  

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Error circuit (contd)

• For larger number of outputs at the gate level,
  pMOS error detectors can be combined using nMOS
  OR circuits
• N pMOS
  NAND - M
  circuits
• 1 nMOS
  OR - N
  circuit
• Maximum number of
  the sampled
  outputs
  equal to
  NM
  
  

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Error Circuit (contd)

• separated error circuits for
  non-inverting and inverting
  outputs
• not needed for the levels
  without dual gates (reduces
  simulation time)
• outputs of both polarities
  are scanned in two
  consecutive
  cycles odd/even
• error circuit may take only set of the worst-case
  outputs (not all of them)

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Error Circuit - Timing Diagrams
The worst-case output at the level i has to fully
evaluate before the evaluation phase of the clock
for the i1 level
Delays are not matched - error is detected
Delays are matched - no error
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6-bit Binary Counter

• the binary counter generates input combination to
  PDE (bit5..0)
• delay is inversely proportional to the count
  of the counter
• when enab(i) becomes low the counter keeps
  previous state
• for levels with dual gates, the counter changes
  its state every other cycle
• minimum possible delay through PDE is determined
  by the vector 1.11 ovfl 1 disables the
  counter

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Counter Enable Controller (CEC)

• each stage has OR
  gate and 2 D
  flip-flops
• initially en signal
  of the first stage is
  set to 1
• en(i) is changed
  at the falling edge
  of the last level clk
• detected error err(i) or count
  overflow ovfl(i) disables the
  level i

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Counter/Controller - Timing Diagrams
fixed combination for the i level
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Simulation results

• t481 MCNC benchmark is simulated
• 4 levels of logic, 3 PDEs, 3 counters
• needs approximately 100-150 cycles to tune itself
  (for 100 MHz clock - about 1.5ms)
• randomly generated capacitances at all gate
  output nodes (can increase gate delay 50-75)
• added capacitance simulates process and
  environment variations that can increase gate
  delay
• goal verify the self-tuning process and look for
  the margins (clock delay vs. worst-case gate
  delay)
• 10 different simulations performed

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Simulation results

• margin ((clock_delay(i) - worst case
  gate_delay(i)) / worst case gate_delay(i)) 100