Compact Modeling project presentation

1
MOS Model 20
A.C.T. Aarts, A. Tajic and D.B.M. Klaassen
Eindhoven University of Technology (TU/e)
NXP Research
2
Contents

• introduction
• physics and features
• results
• versions, source code, documentation

3
Introduction LDMOS devices
LV-LDMOS
HV-LDMOS
4
Introduction LV-LDMOS Modeling
G
D
S
B
5
Introduction LV-LDMOS Modeling
G
MM 11
MM 31
D
S
B
MM11 to model channel region, normal MOS
device MM31 to model the extended drift region
6
Introduction LV-LDMOS Modeling
G
MM 11
MM 31
D
S
B
Di internal-drain node
7
Introduction LV-LDMOS Modeling
G
MM 20
D
S
B
Di calculated inside model
advantage controlled voltage / convergence
8
Introduction HV-LDMOS Modeling
G
B/S
D
9
Introduction HV-LDMOS Modeling
G
MM11
MM31
B/S
D
Rd
10
Introduction HV-LDMOS Modeling
G
MM11
MM31
B/S
D
Rd
G
B/S
D
11
Introduction HV-LDMOS Modeling
G
MM11
MM31
B/S
D
Rd
G
MM31
MM11
B/S
MM31
D
12
Introduction HV-LDMOS Modeling
G
MM20
B/S
MM31
D
13
Introduction LDMOS models

• MOS Model 20
• describes channel region drift region under
  thin gate oxide
• basis building block for broad range of LDMOS

MOS Model 31 describes junction isolated drift
region MOS Model 40 describes drift region on
SOI
14
Contents

• introduction
• physics and features
• results
• versions, source code, documentation

15
MOS Model 20 physics and features

• surface-potential based
• DC-, AC and nodal charge model
• 1/f, thermal, gate-induced noise model
• avalanche model
• geometry (length width) scaling
• temperature scaling
• self-heating
• excellent convergence behaviour
• simulation times equal to sub-circuit models

16
MOS Model 20 physics and features
Di

• drift region
• accumulation
• depletion
• bulk current
• mobility reduction due to
• vertical electric field
• velocity saturation
• avalanche

• channel region
• mobility reduction due to
• vertical electric field
• velocity saturation
  
• channel length modulation
• DIBL static feedback
• avalanche

17
Contents

• introduction
• physics and features
• results
• versions, source code, documentation

18
MOS Model 20 some results
12V SOI-LDMOS Tox 38 nm, W 17 mm, L 1.6 mm,
T 25 oC
IDS mA
gDS mA/V
8
VGS 12V
VSB0 V
6
VGS 9V
4
VGS 6V
2
VGS 3V
0
0
2
4
6
8
10
VDS V
19
MOS Model 20 some results
60V SOI-LDMOS Tox 38nm, W 20mm, L 2.6mm,
Llocos 3.5mm, T 25 oC
including quasi-saturation
without quasi-saturation
IDS mA
10
VGS12V
8
VGS10V
6
VGS8V
4
VGS6V
2
VGS4.4V
VGS3.4V
VGS2.4V
0
2
8
12
0
4
10
6
VDS V
20
MOS Model 20 some results
measured
old model
new model
avalanche current modelling is improved
21
MOS Model 20 some results
14V SOI-LDMOS Tox 60 nm, W 50 mm, L 5 mm,
T 25 oC
CGG fF
CGG fF
VGS V
VDS V
22
MOS Model 20 some results
14V SOI-LDMOS Tox 60 nm, W 50 mm, L 5 mm,
T 25 oC
CGD fF
CGD fF
VDS 0V
VGS 9V
VDS 5V
VDS 14V
VGS 5V
VGS V
VDS V
23
MOS Model 20 more results

• CMC 2006 minutes and presentations

www.eigroup.org/cmc/minutes/2q06_presentations/cmc
_mm20_www.pdf
www.eigroup.org/CMC/minutes/3q06_presentations/ove
rview.pps
www.eigroup.org/CMC/minutes/3q06_presentations/mm2
002_update.pdf

• IEEE Trans. Electron Devices

• A. Aarts, N. DHalleweyn, R. v. Langevelde,
• A surface-potential-based high-voltage compact
  LDMOS
• transistor model, Vol. 52, No. 5, 2005
• A.C.T. Aarts and W.J. Kloosterman
• Compact modeling of high-voltage LDMOS
  Devices including
• quasi-saturation, Vol. 53, No. 4, 2006

24
Contents

• introduction
• physics and features
• results
• versions, source code, documentation

25
source code

• C-code
• SimKit 2.3, level version 2002.0
• old avalanche model, no self-heating
• available http//www.nxp.com/Philips_Models/high
  _voltage/model20
• SimKit 2.4, level version 2002.1
• improved avalanche model, no self-heating
• available http//www.nxp.com/Philips_Models/high
  _voltage/model20
• (since MOS Model 20, level 2002, is a test
  version,
• no attention is paid to backwards
  compatibility)
• SimKit 2.5, level version 2002.X
• improved avalanche model self-heating
• to be released at the end of March 2007

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source code

• Verilog-A code
• original VA-code made by Geoffrey Coram (Analog
  Devices) based on
• documentation of level 2002.0, including
  self-heating
• alignment of VA-code with C-code by Alireza
  Tajic (NXP Semiconductors),
• ongoing
• improved avalanche model has been added
• parameter clipping has been added
• DC analyses in agreement with C-code
• AC analyses in agreement with C-code except at
  Vds0
• transient analyses not tested yet
• noise analyses not tested yet
• VA-code will be released to CMC membership

27
comparing C-code VA-code DC characteristics
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comparing C-code VA-code AC characteristics at
Vds0
29
comparing C-code VA-code AC characteristics at
Vds1 mV
30
model documentation

• some errors in documentation have been found
  (see CMC meeting Oct. 06)
• recently updated model documentation, including
  the improved avalanche
• model, available at
• http//www.nxp.com/acrobat_download/other/philipsm
  odels/m2002.pdf
• Note the link http//www.nxp.com/acrobat_download
  /other/philipsmodels/prtn2005_00406.pdf
• has NOT yet been updated
• corrections to the model documentation, to be
  updated in March 2007
• in Eq.(8.90) FBT must be replaced by FBDT
• Eq.(8.213) should read

31
Summary

• MM20 usable for wide variety of HV-MOS
  
• LV-LDMOS only MM20
• HV-LDMOS subcircuit MM20 serves as core
• MM20 gives accurate results for all regimes of
  operation
• MM20 tested in many different circuits
• excellent convergence behaviour
• MM20 source code documentation available

32
TU/e
technische universiteit eindhoven
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MOS Model 20 must have list
accurate DC/AC derivatives of terminal currents
and node charges charge conservative voltage-drop
across source- and drain
1a
OK
OK
OK
drain OK
drift region resistance, incl. velocity saturation
1b
OK
drift region capacitance
1c
OK
parasitic effects
1d
via sub-circuit
1/f, thermal, gate-induced noise
1e
OK
34
MOS Model 20 must have list
Vsupply up to 200V T 50 till 200 oC
2
OK, till 100V
OK
self-heating and temperature-dependence parameters
3
OK
quasi-saturation, and gm fall-off
4
OK
CGD drop
5
OK
source-drain resistances, and junctions
6
via sub-circuit
OK
substrate current
7
35
MOS Model 20 must have list
geometry scaling, with one parameter set drift
region length as parameter
8
OK
can be added
reverse working (VDS lt 0)
9
OK
both p-type and n-type
10
OK
breakdown behaviour
11
X
good convergence in circuit simulation
12
OK