UltraDense Sensor Networks Statistical Computation and Communication

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Ultra-Dense Sensor Networks Statistical
Computation and Communication

• Yoda Meeting October 15 2004
• University of California at Berkeley

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How to Use a Million Node Network?
How to Produce a Million Node Network?

• Make nodes cheap
• Sensing (cheap ADC)
• Communication (cheap radios)
• Batteries (low power consumption)
• Make em small

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Can We Make Real Smart Dust?
How low can we push power, cost, size?

• Absolutely! By going completely non-traditional!
• Ultra-dense networks get the nodes closer, use
  lots of them, and make their energy consumption
  absolutely minimal (this is lt 10 mW).
• Use non-tuned mostly passive radios center
  carrier frequency randomly distributed
• Use statistical distribution to ensure reliable
  data propagation
• Leads to smart surfaces intelligent walls,
  (strain-stress) sensitive plane wings, adaptive
  construction materials

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ProposalReliable Communications built on top of
ultra-cheap, low power, small
computation/communication nodes

• Goal nodes of 10 mW, 10 mm3, 1 cent
• How
• Low voltage operation (lt 250 mV)
• Absolutely no tuning
• Extensive use of advance passives
• Use statistical networking and density to provide
  reliability

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Energy/Power as the Limiting Factor
Reasonable Target 100 mW/cm3(/year)
Courtesy Shad Roundy (ANU and UCB)
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The Power of Randomness

• Inherent Randomness
• Channels are unreliable
• Changing multipath environment
• Short time constants
• Nodes are unreliable
• May move
• May run out of energy
• Exploiting randomness to provide robustness
• Randomized opportunistic routing provides spatial
  diversity pick any node that is available and is
  in the right direction
• Random duty cycling of nodes to preserve energy
• Cost and size reduction add another layer of
  uncertainty
• Tuning a radio is expensive from an energy and
  integration perspective
• Use redundancy in connectivity grid to avoid
  tuning all together

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Towards a Sub-100 mW IntegratedWireless Node

• Ultra Low-Power/Voltage Design

Power Supply Network
Baseband (mixed-signal)
ClockGeneration
RF Antenna
DigitalProcessor
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Ultra-Low Power Radios
fbb

?
?

• Full integration of everything but antenna
• Can choose any fbb
• Tx/Rx distribution systematic offset
• Suitable for the most standard/exotic processes
  (CMOS, printable circuits?)

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The Roadmap to Ultra-dense Networks
Super-regenerative lt 500 mW
Resonant bodyFinfet
NEMS?
Untuned mostly passive lt 5 mW
Untuned Subthreshold lt 50 mW
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Energy-efficient Transmitters

• Power Oscillator to deliver power efficiently and
  reduce driver power (self-driven)
• FBAR Reference Oscillator
• Concurrent Antenna/Power Oscillator design to
  provide optimal load termination
• Power Control for optimal radiated power
• Frequency Calibration to minimize locking power

Injection-locked transmitter
Core Devices
7-bits capacitive array
TX at 2 mW or less (when on)
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The Next Step in Receiver Design
Sub-threshold RF oscillatorusing integrated LCs
Lower parasitics
Lower parasitics
2 different inductors
Higher Q
2.4 nsec startup
Should enable Sub-100 mW receivers
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Resonant Body Transistor
Drive electrode (-Vg)
Undoped Channel

• Same structure as Double-ended tuned fork
  resonators, but none of the problems
• Accumulate drive tine (doesnt affect Ids)
• Invert sense tine
• During resonance, tox changes, modulates Ids
• No feedthrough problems!

Ids modulated by tine motion
N S/D
Sense electrode (Vg)
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Fusion Technology
Gate becomes Drive/Sense Electrodes
Gap formed by gate oxidation HF release

• Take advantage of FinFET structure and processes
• E-Beam Litho
• HSQ 30nm ln/sp
• Split gate electrode
• Gate oxidation

Thin tines defined by E-Beam litho
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Prototype Device
Metal-Poly Contacts
Metal-Substrate Grounding contacts
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Ultra-Low Voltage Digital Design

• Aggressive voltage scaling the premier way of
  reducing power consumption
• Performance not a dominant factor, yet needs to
  be addressed (dont leave anything on the table)
• Our goals design at 250 mV or below
• Challenges
• Wide variation in gate performance due to
  variability of thresholds and device dimensions
• Process variations make reliable storage at these
  voltages hard
• Sensitivity to dynamic errors due to noise and
  particle-caused upsets (soft errors)
• ? Explore circuit and architecture techniques
  that deal with performance variations and are
  (somewhat) resilient to errors!

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Energy Savings
Data for 4-bit adder (130nm CMOS) obtained
using Monte-Carlo simulations.
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Price to Pay at Low Voltages
Variability
Performance

• Data Preservation memory failure and instability

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Design at or below 300mV Power vs. Reliability
New design methodology that is variation-tolerant
Logic
Vdd lt300mV
Memory
Circuit and architecture techniques to enhance
reliability
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A Self-adapting Approach

• Motivation Most timing variations are
  systematic, and can be adjusted for at start-up
  time using one-time calibration!
• Relevant parameters Tclock, Vdd, Vth
• Vth control the most effective and efficient
  at low voltages
• Can be easily extended to include
  leakage-reduction and power-down in standby

Vdd
Test inputsand responses
Module
TestModule
Tclock
Vbb

• Achieves the maximum power saving under
  technology limit
• Inherently improves the robustness of design
  timing
• Minimum design overhead required over the
  traditional design methodology

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A Self-Adapting Approach

• Process variations are calibrated at startup time
  by built-in self-test
• Timing is controlled by Vth tuning
• Improves yield while saving energy
• Needs Globally Asynchronous communication between
  modules

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Some other aggressive solutions
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The Logic Challenge

• Low-voltage Static CMOS Hard to resolve two
  competing goals
• Sub-threshold operation yields huge performance
  penalty
• Keeping threshold as small as possible is
  desirable, yet leads to unacceptably large
  leakage currents
• Some options
• Use only complex logic gates to benefit from the
  stack effect this might not be always easy and
  overall impact questionable
• Avoid power and ground connections that is,
  think about non-restoring logic. GIVE UP ON NOISE
  MARGIN
• Could be accomplished in pass-transistor logic
• Only Vdd and GND connections in Flip-flops or
  registers act as leakage regulators
• Impact of non-restoration could be resolved by
  adding redundancy
• Plenty of opportunity for ingenuity

R2
R1
Pass-tor chain (low vt)
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The Memory ProblemData-Retention Voltage (DRV)
of SRAM
VTC of SRAM Cell Inverters
when VddDRV
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Further Reduction of DRV

• Sizing 3x PMOS size ? 30mV
• Redundancy for systematic variations (e.g., row
  effect due to layout non-uniformity)
• ECC for random variations!!
• Also helps for soft errors
• Price for all these
• Area, Power, and Delay
• Together, DRV can be reduced to 100mV (from
  current 250mV).

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The plan

• Design small protocol processor for statistical
  networking. Only function would be to collect
  incoming packets, perform some decoding/coding
  and send the new packet back out.
• Combines FSM, some memory and coder/decoder
  logic.
• Start with design and exploration of individual
  building blocks.
• Use 90 nm technology reduce thresholds using
  forward biasing.
• Hopefully could lead to a number of EE241
  projects in spring.

f1
I1
f2
To TX
Decode/code
I2
O
f3
Packetize/serialize
I3
From BB
Queue/de-packetize
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Reducing the Clock Power
Co-design of an integrated CMOS/MEMS 16MHz
reference oscillator (in collaboration with E.
Quevy BSAC)
VP3.3V Lx 0.2015H Cx0.4822fF
Rx2.044kW Rp1MW Q10,000
Electrostatic Gap 50nm Process Sacrificial Ge
Blade process
Received Best Technology Price at Recent Haas
Business Plan Competition
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Reducing The Clock Power
MEMS resonator die flips directly onto CMOS for
low interconnect parasitics and a compact,
integrated clock module.
Resonator outline
Series Osc
Parallel Osc
Ultra-low power (1 mW)
Low-phase noise
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Powering Ultra-Dense Networks
Needs integrated meso-scale energy train
Micro-battery
Electrostatic MEMS vibration converters
Proposal submitted to NSF (PIs Rabaey, Wright,
Sanders, Steingard, Roundy)
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Summary

• Ultra-dense self-contained sensor networks can
  be realized by combining
• Statistical networking and communications
  techniques
• Untuned integrated low-voltage RF making
  aggressive use of integrated passives
• Aggressive low-voltage design (lt 250 mV) for
  baseband analog and digital
• Integrated power and clock sources
• Advanced packaging techniques (2.5D, 3D)

Chip-on-chip oscillator
Collaborative effort with Agilent (R. Ruby)

• Needs progress and advancement in many areas
• Is an excellent example of an alternative
  architecture of the style that may become
  prevalent in the nano era.