Instructor: Nachiket M. Kharalkar

1
Introduction to Microcontrollers

• Instructor Nachiket M. Kharalkar
•  
• Lecture 10
• Date 06/22/2007
• E-mail knachike_at_ece.utexas.edu
•  

2
Todays Agenda

• Exam 1 June 25th
• Review Exam 1
• Finite state machine
• Lab 3 Traffic light controller

3
Definitions

• volatile, nonvolatile, RAM, ROM, port
• basis, nibble, precision, decimal digits (see
  table in next slide)
• overflow, ceiling and floor, drop out,
• bus, address bus, data bus,
• memory-mapped, I/O mapped
• bus cycle, read cycle, write cycle,
• IR, EAR, BIU, CU, ALU, registers,
• reset vector

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Few basic things to memorize

• 22 4
• 23 8
• 24 16
• 25 32
• 26 64
• 27 128
• 28 256
• 29 512
• 210 1024 103
• 211 2048
• 212 4096
• 213 8192
• 214 16384
• 215 32768
• 216 65536
• 162 256
• 163 4096
• 164 65536

6
Number conversions, 8-bit (fill in the blank)

• convert one format to another without a
  calculator
• signed decimal e.g., -56
• unsigned decimal e.g., 200
• binary e.g., 11001000
• hexadecimal e.g., C8
• I wont ask you to convert signed binary or
  signed hex
• signed binary e.g., -00101111
• signed hexadecimal e.g., -2F

7
Details of executing single instructions

• 8-bit addition, subtraction yielding result, N,
  Z, V, C (like HW1)
• simplified cycle by cycle execution
• assembly listing to execution cycles (Lab 2) for
  example for indexed mode addresses,
• ldaa 4,x
• ldaa 40,x
• ldaa -4,x
• ldaa -40,x
• ldaa 400,x
• ldaa 4,x
• ldaa 4,-x
• ldaa 4,x
• ldaa 4,x-
• calculate effective address
• go from assembly to machine code xb
• go from machine code xb to assembly
• simple multiply and divide (mul idiv fdiv)

8
Simple programs (look at assembly code in Chap
1,2,3)

• set reset vector
• specify an I/O pin is an input
• specify an I/O pin is an output
• clear an I/O output pin to zero
• set an I/O output pin to one
• toggle an I/O output pin
• check if an I/O input pin is high or low
• e.g., if PA4 is low then make PB2 high
• 8-bit operations
• add, sub, shift left, shift right, and, or, exor
• simple if-then like examples in Chapter 3
• simple while-loop like examples in Chapter 3

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• it is important to know
• precision (e.g., 8-bit, 16-bit)
• format (e.g., unsigned, signed)
• unsigned, bhi blo bhs and bls
• signed, bgt blt bge and ble
• It takes three steps
• read the first value into a register
• compare the first value with the second value
• conditional branch

10
16-bit timer

6812 timer ports.
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PR2 PR1 and PR0 define the TCNT clock period
12
Fixed time delay software using the built-in
timer

• Timer_Init
• Initialize Timer
• Input none
• Outputs none
• error none
• Timer_Init
• movb 80,TSCR1 enable TCNT
• movb 00,TSCR2 divide by 1
• rts
• Timer_Wait
• Time delay function
• Input RegD time to wait (125ns cycles)
• Outputs none
• error input must be less than 32767
• Timer_Wait
• addd TCNT TCNT at end of delay
• Wloop cpd TCNT is EndTltTCNT
• bpl Wloop
• rts

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Example

• assume TCNT 31 (can be any value),
• Reg D 4000 (means 1ms, in 250-ns units)
• the addd will make RegD 4031 (remains fixed for
  the rest of the subroutine)
• Run square.rtf, with a ScanPoint on Wloop
• RegD-TCNT
• CCRsXhInzvc RegD4031 TCNT34 3997
• CCRsXhInzvc RegD4031 TCNT40 3991
• CCRsXhInzvc RegD4031 TCNT46 3985
• CCRsXhInzvc RegD4031 TCNT52 3979
• CCRsXhInzvc RegD4031 TCNT4000 31
• CCRsXhInzvc RegD4031 TCNT4006 25
• CCRsXhInzvc RegD4031 TCNT4012 19
• CCRsXhInzvc RegD4031 TCNT4018 13
• CCRsXhInzvc RegD4031 TCNT4024 7
• CCRsXhInzvc RegD4031 TCNT4030 1
• CCRsXhINzvC RegD4031 TCNT4036 -5

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• Timer_Wait10ms
• time delay
• inputs RegY is the number of 10ms to wait
• outputs none
• errors RegY0 will wait 655.36 sec
• CYCLES10MS 315 Run mode in real 9S12C32
  10000us/32us, if TCNT32us
• Timer_Wait10ms
• ldd CYCLES10MS
• bsr Timer_Wait
• dbne Y,Timer_Wait10ms
• rts

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New topics from this slide(not for exam 1)
16
Board Demo

• http//www.ece.utexas.edu/valvano/S12C32.htm
• For more information on using the board to
  develop assembly programs seehttp//www.ece.utexa
  s.edu/valvano/EE319K/CW12asm.pdf

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Abstraction

• Software abstraction
• define a problem with a set of basic abstract
  principles
• separate policies mechanisms
• The three advantages of this abstraction are
• 1) it can be faster to develop
• 2) it is easier to debug (prove correct) and
• 3) it is easier to change

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Finite State Machine (FSM)

• A finite state machine (FSM) or finite automaton
  is a model of behavior composed of states,
  transitions and actions.
• inputs, outputs, states, and state transitions
• state graph defines relationships of inputs and
  outputs
• There are two types of FSMs
• Acceptors/Recognizers and
• Transducers

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Acceptor FSM

• This kind of machine gives a binary output,
  saying either yes or no to answer whether the
  input is accepted by the machine or not.
• All states of the FSM are said to be either
  accepting or not accepting.

http//en.wikipedia.org
20
Transducer FSM

• Transducers generate output based on a given
  input and/or a state using actions.
• They are used for control applications.
• It can be further classified into following two
  types
• Moore FSM and
• Mealy FSM

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Moore FSM

• Output value depends only on the current state,
  and inputs affect the state transitions
• Significance is being in a state
• input when to change state
• output how to be in that state
• The advantage of the Moore model is a
  simplification of the behavior.

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Moore FSM
23
Mealy FSM

• Output depends both on the current state and the
  inputs.
• inputs affect the state transitions.
• significance is the state transition
• input when to change state
• output how to change state
• The use of a Mealy FSM leads often to a reduction
  of the number of states.

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Mealy FSM
25

• data structure embodies the FSM
• multiple identically-structured nodes
• statically-allocated fixed-size linked structures
• one-to-one mapping FSM state graph and linked
  structure
• one structure for each state
• linked structure
• pointer (or link) to other nodes (define next
  states)
• table structure
• indices to other nodes (define next states)

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A simulated traffic intersection interfaced to
MC68HC11
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Traffic light controller using the Moore FSM
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• org 3800 variables go in RAM
• StatePt rmb 2 Pointer to the current state
• org 4000 Put in ROM
• Out equ 0 offset for output value
• 2 bit pattern stored in the low part of an 8
  bit byte
• Wait equ 1 offset for time to wait
• Next equ 2 offset for 4 next states
• Four 16 bit unsigned absolute addresses

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• org 3800 variables go in RAM
• StatePt rmb 2 Pointer to the current state
• org 4000 Put in ROM
• Out equ 0 offset for output value
• 2 bit pattern stored in the low part of an 8
  bit byte
• Wait equ 1 offset for time to wait
• Next equ 2 offset for 4 next states
• InitState fdb S1 Initial state
• S1 fcb 01 Output
• fcb 5 Wait Time
• fdb S2,S1,S2,S3
• S2 fcb 10 Output
• fcb 10 Wait Time
• fdb S3,S1,S2,S3
• S3 fcb 11 Output
• fcb 20 Wait Time
• fdb S1,S1,S2,S1
• org 5000 programs go in ROM

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• To add more complexity
• (e.g., put a red/red state after each yellow
  state),
• we simply increase the size of the fsm
  structure
• define the Out, Time, and Next pointers
• To add more output signals
• (e.g., walk light),
• use more of Out field.
• could increase the precision of the Out field
• To add two input lines
• (e.g., walk button),
• increase the size of Next8.
• size 2(number of inputs)

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Lab 3 Traffic Light controller
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• / Port C bits 1,0 are sensor inputs,
• Port B bits 5-0 are LED outputs /
• const struct State
• unsigned char Out //Output to Port B
• unsigned short Time //sec to wait
• const struct State Next4 // Next if
  input00,01,10,11/
• typedef const struct State StateType
• define goN fsm0
• define waitN fsm1
• define goE fsm2
• define waitE fsm3
• StateType fsm4
• 0x21,30,goN,waitN,goN,waitN, // goN
• 0x22, 5,goE,goE,goE,goE, // waitN
• 0x0C,30,goE,goE,waitE,waitE, // goE
• 0x14, 5,goN,goN,goN,goN // waitE
• StateType Pt // Current State
• void main(void)
• unsigned char Input