SiliconCraft, Inc.

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Introducing SiliconCrafts Timing and Power
Solutions
NeoPower
timing and power optimization for high-end VDSM
designs
January 2002
http//www.siliconcraft.com

• SiliconCraft, Inc.

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Introducing SiliconCrafts Timing and Power
Solutions
NeoPower
timing and power optimization for high-end VDSM
designs
Contents
1. NeoPOWER design flow
2. NeoPOWER data flow
3. NeoPOWER features
4. NeoPOWER functions
SiliconCraft, Inc.
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NeoPOWER in Design Flow - I
Timing and power optimization for full-custom
design
PR
parasitic placement info
circuit optimization
block characterization

• SiliconCraft, Inc.

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NeoPOWER in Design Flow - II
Process migration
source design rule
source design
target design rule
user constraints
Extract
resizing
NeoPOWER
timing power
compaction
Target Design

• SiliconCraft, Inc.

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NeoPOWER in Design Flow - III
Timing and power optimization for cell-level
design
initial design
user constraints
with or without any library
NeoPOWER
Automated Transistor Layout
new cells
gate-level PR

• SiliconCraft, Inc.

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NeoPOWER Data Flow
netlist
constraints
switching activity file
NeoTIME timing engine
Short-circuit power optimization
NeoPOWER
sizing engine
timing verification
Optimized circuit

• SiliconCraft, Inc.

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NeoPOWER Features

• Today's big, fast designs make timing and power
  critical concerns through all steps in the IC
  design flow, and demand more than ever from the
  designer's tool kit.
• SiliconCraft also introduces NeoPOWER, a
  transistor-level circuit optimization product
  with improved transistor sizing technology.
• By considering upsizing effects of all critical
  paths of a circuit as well as the worst case
  delay path, NeoPOWER provides effective
  optimization results in reduced runtime with
  guaranteed convergence.

• SiliconCraft, Inc.

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NeoPOWER Key Features

• Circuit optimization for high performance low
  power designs
• Embedded timing engine
• Short-circuit power optimization
• User controls

• SiliconCraft, Inc.

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NeoPOWER Key Features - I
Optimization

• Circuit optimization for high performance low
  power designs
• power speed area constraints
• fast static power estimation
• simultaneously optimize for timing area or
  timing power
• links to layout

Others
NeoPOWER
timing only
original
original
Power
Power
timing power
power only
Delay
Delay

• SiliconCraft, Inc.

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NeoPOWER Key Features - II
Embedded Timing Engine

• Automatic technology file generation for timing
  accuracy
• NeoTIME timing engine
• At each transistor sizing iteration, timing
  effect is propagated
• Automatic setup and hold violation check

• SiliconCraft, Inc.

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NeoPOWER Key Features - III
Short circuit power optimization

• Short circuit power optimization by
• Automatic detection of slow nodes causing short
  circuit
• Removal of such nodes by transistor sizing
• You can trigger short circuit power optimization
  by
• OptimizeCircuit shortcircuit y

• SiliconCraft, Inc.

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NeoPOWER Key Features - IV
User Controls

• Circuit delay by imposing clock constraints
• Minimum and maximum size of transistors
• Bump-up size
• No sizing control for given Cells, FETs, and
  Instances
• Number of generated new cells
• NeoPOWER outputs either flat or hierarchical
  netlist
• In n-level hierarchy mode
• Verilog, SPICE
• Cell number control particular cell or total
  number of cells

• SiliconCraft, Inc.

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NeoPOWER Functions

• NeoPOWER files
• Definition and declaration
• OptimizeCircuit
• Command summary I
• Command summary II

• SiliconCraft, Inc.

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NeoPOWER Functions - Files

• Input files
• Input data netlist
• TimingModel file
• Technology file
• Command file
• Output files
• Optimized netlist
• Log file
• Latch information and blocked node file

• SiliconCraft, Inc.

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NeoPOWER Functions Definintion and Declaration

• Input/output port timing constraint INPUT,
  OUTPUT
• INPUT input_nodes clock_node clock_edge rise_max
  fall_max rise_min fall_min
• OUTPUT output_node clock_node clock_edge
  rise_setup fall_setup rise_hold fall_hold
• Clock definition CLOCKDEF
• CLOCKDEF node_name RDELAYvalue FDELAYvalue
  RSLOPEvalue FSLOPEvalue PERIODvalue
• Latch definition Latch
• Latch latch_cell
• Latch latch_node
• Latch Feedback_tx(s)

• SiliconCraft, Inc.

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NeoPOWER Functions OptimizeCircuit

• OptimizeCircuit setBumpSize ltfloatgt
  -slackGuard ltfloatgt -maxSelect ltintgt
  setGridSize -ltfloatgt -shortCircuit y
• -plot lty/ngt
• -setBumpSize Specify bumping up size during
  sizing
• Default is 0.2u
•   -slackGuard Set slack guard for timing error in
  neopower
• and value 1.0 means 100
•   -maxSelect maximum count of transistors during
  sizing
• Default is 1
•   -setGridSize During optimization transistor
  sizes are rounded off to a value which is the
  closet multiple of the value defined.
• Default is 0.1u  
• -plot Plot cost-delay curve

• SiliconCraft, Inc.

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NeoPOWER Functions Command Summary I

• Alias
• BlockArc
• BlockCellInstance
• BlockCellNode
• BlockInstance
• BlockNode
• ClockDef
• FindRegConstraints
• GetNodeValue
• Help
• Input
• IncludeFile
• Latch
• OptimizeCircuit

• SiliconCraft, Inc.

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NeoPOWER Functions Command Summary II

• Output
• ProhibitCellFromSizing
• Quit
• ReadNetList
• ReadSwitchingActivity
• ReadTechnologyFile
• ReadTimingModel
• SetDirection
• SetFetWidth
• SetPNRatio
• SetPNRatioInCells
• SetNodeValue
• WriteSizedSpice

• SiliconCraft, Inc.