Design Productivity Crisis

1
Timing Analysis and Optimization Implications of
Bimodal CD Distribution in Double Patterning
LithographyKwangok Jeong and Andrew B.
Kahng VLSI CAD LABORATORY UC San
Diego http//vlsicad.ucsd.edu/ Research
supported by STARC ASP-DAC Session 5B, January
21, 2009
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Motivation

• Single exposure lithography
• All shapes printed by one exposure
• Adjacent identical features have same mean CD
  (critical dimension), and spatially correlated CD
  variations
• Double patterning lithography (DPL)
• Shapes are decomposed and printed in two
  exposures
• Adjacent features can have different mean CD, and
  uncorrelated CD variations
• ? New set of bimodal challenges for timing
  analysis and optimization

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DPL Approaches

• Print lines
• Misalignment ? No CD difference between two
  adjacent lines
• CD control is key factor

• Print edges
• Exposure difference ? No CD difference between
  two adjacent lines
• Overlay control is key factor

1st Exp.
2nd Exp.
Resist
Poly
CD variation w/o misalignment
1st Exp.
2nd Exp.
1st Exp.
2nd Exp.
CD variation w/ misalignment
Final patterns
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Bimodal CD Distribution

• Two CD distributions and Two different colorings
  ? Two different timings
• This Research
• Assess potential impact of bimodal CD
  distribution on timing analysis and guardbanding
• Cell delay and power, path delay, clock skew,
  path timing slack
• Seek potential solutions to minimize the impact
  of bimodal CD distribution

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Impact on Path Delay Variation

• Simulation setup
• 45nm PTM, Typical corner (TT), 1.0V, 25 C
• 16 stages of 45nm INVX4 (Nangate Open Cell
  Library)
• Each cell can have two different colorings
• Each color (Mask 1 or 2) can have two different
  process results (Min or Max)

Covariance worsens path delay variation

• Simulation results
• Mean and sigma of a long inverter chain (16
  stages)over all process corners (Min and Max
  combinations)
• Alternately-colored paths ?smaller path delay
  variation

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Impact on Timing Slack (Analysis)

• Timing slack calculation
• Timing slack
• Timing slack variation
• Clock skew
• Especially, clock skew from uncorrelated
  launching and capturing clock paths are the major
  source of timing slack variation.
• Example

Large correlation is better for timing slack
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Impact on Timing Slack (Simulation Setup)

• Testcase
• AES from Opencores, Nangate 45nm library, PTM
  45nm
• Extracted critical path

• Exhaustive tests (4 x 254) not feasible, so we
  fix the data path coloring.

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Impact on Timing Slack (Simulation Results)

• Clock skew
• Even for the zero mean difference case, clock
  skew exists and increases with mean difference
• Pooled unimodal can not distinguish this clock
  skew

• Timing slack
• Originally zero slack turns out to have
  significant negative slack
• Pooled unimodal shows very pessimistic slack

53ps
22ps
Cases 1, 2, 5
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Possible Solutions for Timing Optimization

• Self-compensation
• Alternative coloring of timing paths ? reduce
  variation
• Same coloring sequence for clock network ? reduce
  clock skew
• ? But restricted coloring can increase coloring
  conflicts
• Solutions for coloring conflicts
• Candidate1 large sized cells to prevent
  conflicts between cells
• Candidate2 Placement legalization after
  coloring (like UCSD Corr)

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Self-Compensation Is Not Enough

• Self-compensation in path coloring reduces delay
  variation, but bimodal CD impact is still
  significant

Better, but can still have timing violations
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BEOL Compensation of Measured FEOL ?CD

• UCSD Design-Aware Process Adaptation
• FEOL metrology ? intentional BEOL CD biasing
• DPL allows wire segments in different masks to
  change CD independently
• Color interconnects differently for different CD
  groups
• F-factor (in)flexibility factor for
  interconnect coloring, e.g., F1,
• All wire segments connected to CD_group1 gates
  must be in INT_MASK1
• All wire segments connected to CD_group2 gates
  must be in INT_MASK2

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Compensation with BEOL Biasing

• Small CD gates ? thick interconnect (large cap.)
• Large CD gates ? thin interconnect (small cap.)
• Example for F0.8 (80 of interconnects colored
  according to the gate CD groups)

meet timing
Change metal/ILD thickness?
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Conclusions

• Analytical and empirical assessments of DPL
  potential impact on timing analysis error and
  design guardband
• Traditional unimodal analysis may not be viable
  for DPL
• Our analysis 20 or greater change in timing
• Self-compensation strategies, along with BEOL
  biasing, can reduce impact of bimodal CD
  variation
• Work at UCSD Design-Aware Process Adaptation
• Ongoing work more accurate, efficient and
  practical solutions to bimodal-awareness
  challenges in timing analysis and circuit
  optimization

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• BACKUP

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Impact on Cell Delay and Power

• Monte Carlo simulations 10K
• DPL1 (2n-1)-th gate is group1 and 2n-th gate is
  group2
• DPL2 2n-th gate is group1 and (2n-1)-th gate is
  group2
• Unimodal CD distribution covers CDgroup1 ?
  CDgroup2
• Unimodal representation is too pessimistic
• Characteristics of DPL1 and DPL2 are very
  different!

Unimodal
Bimodal group1
Bimodal group2
2n
59
54
61
56
64
66
60
Worst CD
Best CD
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Impact on Design Guardband

• Comparison of required design guardband
• Unimodal approximation conservative but easy
• Lead to over-design
• But can use conventional flow
• Bimodal-aware realistic but complex method
• New bimodal-aware timing analysis and new
  timing-driven design optimizations are required