Design Review July 2004, HCMOS9 Sayf Alalusi

1
Design ReviewJuly 2004, HCMOS9Sayf Alalusi

• 4-Way Phase-Shifter Array
• Stand-Alone Phase-Shifter
• Test Calibration Structures

2
Phase Shifter Array
This Chip

• - Current design implements ¼ of a
• 16-antenna adaptive antenna array
• Fully functional, 4 chips can be used in concert
  to implement full array.
• The output driver power matched to 58ohm (Z0 of
  Tlines)
• Depending on system spec.s the PAs could even
  be considered to be included.
• e.g. -3dBm from one output driver gives an EIRP
  of 21dBm for the array!

3
T-Line Based Design

• Inductive passive components are T-Lines,
  therefore T-Line models are very important
• Transistors were measured in CPW environment, so
  stay with that. Note it is possible that uStrip
  has lower loss, but then transistor S-Parameters
  will be off.
• 3 sets of measured CPW data
• (W10,S2), (W10,S4), (W7,S4.5)
• Use de-embedded measurement data to calibrate
  model.
• 2-stage T-line Model
• HFSS Ports-only soln. (highest accuracy,
  reasonable soln. time and memory usage) to get
  T-line parameters Zo, Keff , Atten.
• Parameters are input to ADS ideal physical
  transmission line. This can be scaled in length.

4
HFSS Setup
Air
Si3N4, 1um, K??
Soln. accu. 0.01
SiO2, M6 ½ um, K??
Si, K11.9, 10 S/m
Port outline is also important !
5
HFSS Ports-Only Solution
Mag. E
DC soln copper conductivity 5.1E7 perfect
cond.
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T-Line Simulations vs. Measurement
Good agreement with measured data gives us
confidence to predict the parameters of new
T-Lines. (Wsignal trace width, Sgap spacing)
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T-Line Prediction W3, S3
- Prediction of W3, S3 CPW fits in well with
other measured data. - Small overall width
allows for tight turns.
lt 20 um
7 um
8
ADS Design Environment

• Transistors are represented by measured S-Param.
  blocks, T-Lines are represented by ideal
  physical transmission lines.
• T-Line params are from HFSS sim.
• Design is optimized over T-Line lengths only.

Text file list of (freq., S-Matrix) pairs.
9
PIC-Based Phase Shifter
out

• PIC Pass Invert Cancel
• Allows for very simple vector modulator.

I
phase shifted output
- 0
I
out-
I-
Q
- 0
Q
Q-
The ordering of the IQ input signals is not
important! So
10
Phase Shifter Transformation

• You can re-arrange the inputs and outputs to
  avoid crossing the signals on M6. This will need
  a package to test 4-Way array.

• The important thing is that any input phase can
  be switched and/or combined with any other, at
  either output node. If I and Q can be generated
  in-line with the input power distribution
  network, the signal lines will never cross, only
  sum at certain points.

11
PIC Circuit Slice

• All transmission lines are accounted for.
• Necessary for tuning
• Also need to provide for physical separation
  between transistors (esp. Common Gate / Pass
  device).
• Direct translation to Layout!
• 2 PIC slices 1 PIC, 2 PICs 1 Phase Shifter

12
10-port Simulation of Phase Shifter
out
Q-
I

• Full Phase Shifter circuit is simulated in ADS
  as a 10-port network.
• This allows discrimination of contributions of
  various signals.
• Actual input signals are not important, can be
  assigned later, at layout.

I
out-
Q-
Q
I-
I-
Q
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ADS Simulation with Tline Models

• Design is optimized in ADS.
• Symmetry is enforced across all PIC slices.
• There are no other resonances between 40GHz and
  DC.

Fwd. Trans. (S21)
Input Match (S11)
Output Match (S22)
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ADS Sims with Tline Variations

• Insensitive to variations in T-line parameters.
• Keff was changed from (nominal) 4.5 to 4.2 to 4.8
• Z0 variation has very little effect.

15
Input Power Division Network

• The input must undergo a 116 split to drive the
  array of 4 phase shifters.
• it must also delay 1/2 of the input signals by 90
  degrees to generate the Q signals.

-90 deg.
S11 -20 dB
Q-
l/4 x-frmr
l/4 x-frmr
I
l/4 x-frmr
S22 -7 dB
The impedance at this point should be real, so
that the 90 deg. delay does not change the
impedance. Allows enforcement of symmetry across
all signal paths
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HFSS Simulation of Power Dividers

• Angle difference is
• /- 90 degrees.
• 0.8 dB extra loss on meander branch (due to
  longer length).
• Keff variation only causes /- 1.5 degrees
  error.
• Note data is from previous version of network.

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End-to-End Simulation (1 of 2)

• Single input through power dividers, I / Q
  generation, and active circuits.

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End-to-End Simulation (2 of 2)
Beam swept, weights quantized Directivity
error Angle error Angle error w/
constellation rotated 90 degrees
19
(No Transcript)
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Power divider, and I / Q generation, input to
active circuits
21
PIC slice circuit Replicated 16x to make 4-way
array
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Testing the 4-way Array

• A package will be required. SyChip and VTT are
  both on-track.

Ph. Sh. Array Chip
I
Balun
I-

• Set antenna array phasing and then sweep a
  reference antenna to measure the pattern.
• Reflections from the environment should be weak
  do not need actual anechoic chamber.

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Package Layout / Pinout

• Possible package layout, showing feasibility of
  single-plane design.

Antenna Array
Power Rails
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Stand-Alone Phase-Shifter

• Need to generate IQ differential all on one side
  in order to use our probe station.

• The design is very robust. Almost any input
  order can be accommodated with the same active
  circuits.

Q-
- 0
I
I-
- 0
G
G
Q
-
S
Rat Race
S
Q-
G
G
- 0
I
I-
- 0
Q
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Stand Alone Phase Shifter
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Rat Race Hybrid / - outputs

• Stand-Alone Phase Shifter
• Active circuits and I / Q generation are
  identical to 4-way array.
• Rat Race hybrids are added to get 2 copies of I
  and I- each.

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Test Calibration Structures

• CPW Open-Short De-embedding sites.
• 2 Rat Race hybrids with each port terminated, to
  see attenuation and phase of each port.
• 2 power dividing / delay networks with each port
  terminated.
• Hakans attenuators.
• others?

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EIRP vs. System Power (1 of 2)
N Pt , Ant. direc. N (e.g. 10)
Unit Pt , Ant. direc. N (e.g. 10)
Unit Pt ,Unit Ant.
d
d
d
N2 (20dB)
N (10dB)
N (10dB)
1 (0dB)
1 (0dB)
1 (0dB)
Equiv. EIRP, but only array can select
direction electronically. Array has lower PA
requirements. 1W_at_500mVp-pgt0.25ohm!
Unit Pt , Ant. Array N10(classical)
N Pt , Ant. Array N10
d
d
N (10dB)
1 (0dB)
N2 (20dB)
N (10dB)
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EIRP vs. System Power (2 of 2)

• Total of 3-4dB loss through power division
  network.
• 3-4 dB of loss through active circuits.
• Grand total of 7-8 dB loss from input to antenna
  output.
• This loss can be regained by just one more amp on
  the input!