Introduction1

1
Introduction-1

• All sequential circuits depends on ordering of
  events.
• In synchronous design, the ordering of events is
  achieved by global clock.
• In synchronous design memory elements in the
  system are simultaneously updated by a globally
  distributed periodic synchronization signal known
  as global clock.
• System functionality is ensured by some strict
  constraints on the clock generation its
  distribution to memory elements.

2
Timing of Integrated Circuits
3
Introduction-2

• digital system designers strive to maximize the
  clock frequency in order to achieve high system
  performance.
• Three ways to do it in synchronous design
• 1. Employ a fast circuit family
• (bipolar ECL / GaAs / CMOS)
• 2. Use faster storage elements(latch/FF) and
  robust clocking scheme
• 3. Distribute clock with small skew

4
Signal Classification

• Criterion How the signal is related to local
  clock.
• Synchronous signal has the exact same frequency
  as the local clock and maintains a known fixed
  phase offset to that clock.
• Mesochronous(meso middle) signal has the same
  frequency as the local clock but unknown phase
  offset w.r. to that clock.
• Plesiochronous(plesio near) signal has
  nominally but slightly different frequency w.r.
  to local clock.
• Asynchronous signal can transition arbitrarily at
  any time(not slave to any local clock).

5
Synchronous Timing
6
Timing Constraintsfor edge triggered flops

• Setup(performance constraint)
• Clock period gt max clk-to-q delay of the source
  flop max logic delay between flops setup time
  of the destination flop.
• Hold(functionality constraint)
• Hold time of the destination flop lt min
• clk-to-q delay of the source flop min logic
  delay between flops.

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Timing Constraintsfor level sensitive latches

• Setup
• Tcycle,min gt Tlatch,max Tlogic,max
  tclk-width,min
• Hold
• Tsetup,max lt Tclk-width lt Tlatch,min Tlogic,min
  Thold,max

8
Clock Uncertainty- SKEW

• Skew is the spatial variation in the arrival time
  of clock transition to different registers.
• The skew between two points I and J is the
  difference between a certain (pos/neg) transition
  of clock at those 2 points.
• It can be positive or negative depending on
  routing direction and position of the clock
  source.
• The main reason of skew is the static mismatch in
  clock paths and difference in clock load.
• Affects both performance and functionality.

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Clock Uncertainty- JITTER

• Jitter is the temporal variation of the clock
  period at a given point on the chip.
• Its a zero mean random variable.
• The absolute jitter is the worst case variation
  of of a clock edge at a given location w.r. to an
  ideally periodic reference clock edge.
• Affects only performance(by reducing available
  clock period)

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Combined Effect of skew and jitter in edge
triggers flop constraints

• Setup(performance constraint)
• Clock period gt max clk-to-q delay of the source
  flop max logic delay between flops setup time
  of the destination flop
• skew 2 absolute jitter
• Hold(functionality constraint)
• Hold time of the destination flop lt min clk-to-q
  delay of the source flop min logic delay
  between flops -- skew - 2 absolute jitter

11
Source of skew and jitter-1
12
Source of skew and jitter-2

• Clock Signal Generation clock signal generation
  itself causes jitter the signal is typically
  generated by analog circuit (VCO) which is
  sensitive to intrinsic device noise and power
  supply variation. A major problem is the
  coupling from the surrounding noisy digital
  circuit through the substrate especially in
  modern fabrication process.

13
Source of skew and jitter-3

• 2. Manufacturing Device Variation buffers are
  integral components in clock distribution
  circuits. Unfortunately, as a result of process
  variation, device parameters in the buffers vary
  along different paths, resulting in static skew.
  Some of the sources are variation in oxide,
  dopant and lateral(width and length) dimension.
• 3. Interconnect Variation Vertical and lateral
  dimension variations causes the interconnect R
  C to vary(static -gt skew) across the chip. One
  important source is the inter-layer
  dielectric(ILD) variation.

14
Source of skew and jitter-4

• 4 5. Environmental Variations
• They are probably the most significant
  contributor to skew and jitter. Two 2 major
  sources are power supply and temperature.
• Temperature gradient across the chip which can be
  quite large results from power supply variation.
  Shutting off parts of the chip by clock gating
  for low power causes large temperature variation.
• Temperature variation is usually considered skew
  component because of its relative slow change and
  may be compensated using feedback
• Power supply voltage which is a strong function
  of switching activity is the major source of
  jitter.

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Source of skew and jitter-5

• High frequency power supply changes are difficult
  to compensate for, even with feedback circuit.
  Consequently, power supply noise fundamentally
  limits the performance of clock networks.
• To minimize power supply, use high performance
  designs and decoupling capacitance around major
  clock drivers.

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Source of skew and jitter-6

• 6 7. Capacitive coupling
• Changes in capacitive load contributes to timing
  uncertainty(jitter).
• 2 major source coupling between the clock lines
  and the adjacent signal wires and the variation
  in gate capacitance of registers.
• For many registers the clock load is a function
  of the current state as well as next state. This
  causes the delay through the clock buffers to
  vary from cycle to cycle.

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Design Technique for dealing with skew and jitter
-1

• Some useful guidelines for reducing clock
  skew and jitter are
• 1.To minimize skew, balance clock paths from a
  central distribution source to individual
  clocking elements, using H-tree structures or
  more generally routed matched-tree structures.
• 2.The use of local clock grids (instead of
  routed trees) can reduce skew at the cost of
  increased capacitive load and power dissipation.

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Design Technique for dealing with skew and jitter
-2

• 3. If data-dependent clock load variations cause
  significant jitter, differential registers that
  have a data-independent clock load should be
  used. The use of gated clocks to save power
  results in a data-dependent clock load and
  increased jitter in clock networks where the
  fixed load is large (e.g., in clock grids), the
  data-dependent variation might not be
  significant.
• 4. If data flow in one direction, route the data
  and the clock in opposite directions. This
  eliminates races at the cost of performance.

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Design Technique for dealing with skew and jitter
-3

• 5. Avoid data-dependent noise by shielding clock
  wires from adjacent signal wires. By placing
  power lines (VDD or GND) next to the clock wires,
  coupling from neighboring signal nets can be
  minimized or avoided.
• 6. Variations in interconnect capacitance due to
  interlayer dielectric thickness variation can be
  greatly reduced through the use of dummy fills.
  Dummy fills are very common and reduce skew by
  increasing uniformity. Systematic variations
  should be modeled and compensated for.

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Design Technique for dealing with skew and jitter
-4

• 7. Variation in chip temperature across the die
  causes variations in clock buffer delay. The use
  of feedback circuits based on delay-locked loops
  can compensate for temperature variations.
• 8. Power-supply variation is a significant
  component of jitter, as it impacts the
  cycle-to-cycle delay through clock buffers.
  High-frequency power-supply variation can be
  reduced by adding on-chip decoupling capacitors.
  Unfortunately, decoupling capacitors require a
  significant amount of area, ad efficient
  packaging solutions must be leveraged in order to
  reduce chip area.

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Self-timed and asynchronous systems

• Functions of clock in synchronous design
• 1. Acts as completion signal
• 2. Ensures correct ordering of events
• Truly asynchronous design
• 1. Completion is ensured by careful timing
  analysis
• 2. Ordering of events is implicit in logic
• Self-times design
• 1. Completion is ensured by completion signal
• 2. Ordering is imposed by handshaking signal

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2 way handshaking
23
4 way handshaking

• Slower but unambiguous

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Synchronizer-1

• Asynchronous signal coming into a synchronous
  system must be synchronized with the rest of the
  system.
• This is generally done by feeding the
  asynchronous signal to a flop referred to as the
  synchronizer.
• A serious concern is the prolonged indecision of
  the synchronizing flop when it enters into
  metastable state(caused by setup/hold violation
  of the asynchronous input signal to the flop) as
  illustrated in the next slide.

25
Synchronizer-2
26
Clock Synthesis and Synchronization using PLL-1

• High frequency clock(in GHz) are almost always
  generated from crystal(less than 200Mhz) by using
  PLL as a multiplier
• PLL is also used to synchronize communication
  between chips.
• The above 2 uses of PLL is shown in the next
  slide.

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Clock Synthesis and Synchronization using PLL-2
28
Distributed Clocking using DLL-1

• A recent trend in high performance clocking is to
  use Delay Locked Loop(DLL) which is a variation
  of PLL.
• DLL corrects phase error by using voltage
  controlled delay line(VCDL)
• The output of the DLL is phase aligned with the
  reference input. Since it takes some time for
  this alignment, DLL can be used to compensate for
  static process variation and slow dynamic
  variation(e.g., temperature).

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Distributed Clocking using DLL-2
30
Distributed Clocking using DLL-3

• DLL approach to clock distribution
• - The chip is partitioned into many small
  regions called tiles.
• - The global clock is distributed to each tile
  through a DLL. The feedback signal to DLL is
  brought after clock tree buffers.
• - In the following figure the clock input to
  Digital Circuit blocks are phase aligned with
  the global clock by using DLL.

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Distributed Clocking using DLL-4
32
Optical Clock Distribution-1

• The performance of a digital design is
  fundamentally limited by by process and
  environmental variations.
• Use optics for system wide synchronization
• The advantage of optical signal is that it is not
  sensitive to temperature and electromagnetic
  interference(cross talk, inductive coupling) and
  clock edges do not degrade over long distances
  (i.e., tens of meters). In fact, it is possible
  to deliver an optical clock signal with at most
  100ps of uncertainty over tens of meters.

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Optical Clock Distribution-2

• The disadvantage is the challenge in designing
  optical receiver(optical to electrical
  conversion). The receiver is susceptible to
  process and environmental variations(hence
  uncertainty) very much like conventional
  electrical approach but the problem is confined
  to receiver, which makes it more tractable.
• Optical clocking has an important future if the
  challenges dealing with process variation in
  opto-electronic circuit can be addressed.

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Optical Clock Distribution-3

• Architecture for optical clock distribution

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GALS

• A promising solution of the increasingly
  difficult problem of clock distribution
  (uncertainty and power dissipation) is to use
  islands of synchronous units connected by an
  asynchronous network called Globally Asynchronous
  Locally Synchronous (GALS) to harness the
  benefits of both approach while keeping the
  difficulties of each approach a minimum.