Dynamic Memory

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Dynamic Memory
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Memory Bit Cells
Each bit is stored in a D latch
Static RAM
Dynamic RAM
Replace Tri-state inverter with a single nMOS
transistor. Use bi-directional bit line.
Reading Dont drive bit line select bit
cell. Writing Externally drive bit line (hi/lo)
select bit cell.
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Destructive Read

• A memory cell is read by discharging the
  capacitor
• Only a small voltage change
• Destroys the value held in the cell!

• A Sense-Amp senses the small voltage changes and
  amplifies them

• Once amplified, the value is written back to the
  memory cell

bit line (long line with lots of capacitance)
write or writeback
?
bit
SA
write
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16-bit DRAM Organization

• DRAMs are organized as square arrays
• ½ address bits for row, ½ for column
• In this 16-bit memory 2 bits for row, 2 for col

Row Enable 0
Row Enable 1
Row Enable 2

• Example Read location 6 (0110)
• Row 01, Col 10

Row Enable 3

• The row is selected first, reading all columns in
  row

Sense Amps

• All bits in row are written back

• The column is then selected at the bottom

ColSel 0
ColSel 2
ColSel 3
ColSel 1
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Refresh

• DRAM loses its charge in a few milliseconds
• Have to re-write every 20ms or so

Row Enable 0
Row Enable 1

• Reading every bit will do (writeback will refresh)

Row Enable 2

• This means 64M reads every 20ms for a 64Mb DRAM

Row Enable 3

• Solution
• Reading just one bit in a row causes all to be
  refreshed!

Sense Amps

• Only sqrt(64M) 8K reads per 20ms

ColSel 0
ColSel 2
ColSel 3
ColSel 1
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DRAM Pinout

• A 64M x 1 DRAM needs
• 26 Address Pins,1 Data Pin,CS,R/W,OE,Vdd, GND
• 26 out of 32 pins are just for the address!

• Break the address up into two parts
• Row and Column
• Load in the Row first, and latch it
• Load in the Column second
• Use RAS and CAS to indicate each half of the
  address

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DRAM timing
Address
Row
Col
RAS
CAS
Data
Data
1. Place Row address on bus, Assert RAS
2. Place Col address on bus, Assert CAS
3. Wait for data to become valid (tRAC), Read Data
4. Wait for writeback to complete (tRC), start
next cycle
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Fast DRAM Access Modes

• Enabling a row reads all the bits of the row
• Stored in SRAM at the column select level

Row Enable 0
Row Enable 1

• Is it possible to read other columns in the open
  row at high speed?

Row Enable 2
Row Enable 3

• Special DRAM modes allow this
• Open one row, then specify which columns to read

Sense Amps

• Spatial locality makes this work
• Caches work especially well

ColSel 0
ColSel 2
ColSel 3
ColSel 1
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Page Mode
Address
Col2
Col3
Col4
Row
Col1
RAS
CAS
Data
D2
D3
D4
D1
Page Mode Fast access within a row
Put Row on bus, assert RAS
Put Col on bus, assert CAS
Without unasserting RAS Unassert CAS, put
new Col on bus and reassert CAS
Repeat for all columns to read in a row
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Memory Speed Analysis

• Traditional memories take the same amount of time
  for all accesses
• Bandwidth 1/latency bus width
• Ex. 50ns latency, 4 bytes wide 1/50ns 4 ? 80
  Mbytes/s

• Page mode and related DRAMs have different
  latencies for different types of accesses
• Latency for first access in row (long)
• Latency for subsequent accesses in row (short)

• Latency is usually expressed for first access
• Bandwidth is usually expressed for others
• Ex 50ns 1st access, 10ns subsequent
  accessesLatency50ns, Bandwidth 1/10ns 4
  bytes wide ? 400Mbytes/s

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Comparison of Asynchronous DRAM types

• Plain DRAM - Access time of 50ns for all accesses

• Fast Page Mode DRAM (FPM) - 50 ns for first
  access in a row, 30ns for subsequent accesses in
  row

• Extended Data Out DRAM (EDO) - 50 ns for first
  access in a row, 20ns for subsequent accesses in
  row

Access to Row DRAM Type 1st 2nd 3rd 4th Average
Plain 50 50 50 50 50ns
FPM 50 30 30 30 35ns
EDO 50 20 20 20 27.5ns
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Comparison of Synchronous DRAM types

• Synchronous DRAMs are synchronized to the
  processors 64-bit memory bus (Front-side Bus)
• Specd in bus cycles instead of nanoseconds

• General rule 5 bus cycles for first access, one
  access per bus cycle after that

• DDR SDRAMs send data on both edges of clock
• 5 or more bus cycles for first access, two
  accesses per bus cycle after that

• Identifiers
• DDR- number is twice the bus speed (e.g. 200MHz ?
  DDR-400)
• PC number is eight times the DDR number (e.g.
  DDR-400 ? PC3200)

Access to Row DRAM Type Bus
speed Bandwidth 1st 2nd 3rd 4th Average PC100
SDRAM 100MHz 800MB/s 50 10 10 10 20ns
PC133 SDRAM 133MHz 1064MB/s 38 7.5 7.5 7.5 15ns
PC1600 DDR2 SDRAM 100MHz 1600MB/s 50 5 5 5 16ns
PC2100 DDR2 SDRAM 133MHz 2100MB/s 38 3.8 3.8 3.8
12ns
PC6400 DDR2 SDRAM 400MHz 6400MB/s 13 1.3 1.3 1.3
4.2ns
PC8500 DDR2 SDRAM 533MHz 8500MB/s 9 0.9 0.9 0.9 2
.9ns
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Memory Type Comparisons
EEROM
ROM
DRAM
SRAM
Slow (read 100ns)(write 4700ns)
Varies
Slow (10ns min access time) Access modes speed up
(DDR SDRAM, etc.)
Fastest(3ns min access time)
Speed
Cheapest
Cheap
Cheapest
Expensive
Price
Non-volatile (may have limits)
Indestructible
Erased on Power off
Erased on Power off
Volatility
Any data that needs to persist after power off
Program memory for special-purpose systems
Large memories for computers
1. High-speed memory2. Small memories
Uses