4HSIC JUNCTION BARRIERSCHOTTKY JBS DIODES

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4H-SIC JUNCTION BARRIER/SCHOTTKY (JBS) DIODES

• Rahul Radhakrishnan
• Masters Technical Paper

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Introduction

• Modern power system trends
• Size reduction
• Higher efficiency
• Fast switching devices
• Rectifier
• Low leakage current
• Low on-resistance
• Fast switching

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Why JBS diode

• Unipolar devices inherently faster
• PIN junction reverse leakage current is lower
• Schottky junction forward resistance is lower
• Junction Barrier Schottky (JBS) diode combines
  both
• Low barrier schottky
• Predominant schottky action at low forward
  currents reduces minority carrier storage
• Reverse depletion region of PIN junction expands
  laterally to pinch-off schottky junction

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Silicon Carbide

• High band-gap (3.2eV for 4-H SiC)
• Low intrinsic concentration of charge carriers
• Lower leakage current
• 10-8/cm3 compared to 1010/cm3 for Si
• Large saturated electron drift velocity
• Faster switching
• Small dielectric constant (9.7)
• High thermal conductivity
• High electron mobility
• So, attractive candidate for power
  semiconductor!

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SiC v/s Si JBS diode

• Higher doped drift region
• Minority carrier injection by PIN part is not
  essential in SiC JBS diodes.
• So, reverse recovery is even better.
• Smaller drift region thickness
• About 10 times higher critical electric field
• Series resistance is thus reduced
• High voltage and current operation

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JBS technology

• Geometrical arrangement of PIN and Schottky parts
  critical
• Schottky part carries forward current decides
  on-resistance
• PIN part limited by fabrication tolerances
• PIN part ideally doesnt turn on at low currents
• Doping and thickness of semiconductor
• Schottky metal
• Overlay metal layers
• Edge termination
• Guard rings
• Junction termination extension

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JBS theory

• On the left, schottky interface carries forward
  current
• On the right, the PN junction depletion region
  widens to pinch off the schottky channels
• Depletion region pinch off only under reverse
  bias
• Schottky barrier is shielded from applied reverse
  voltage by pinch-off

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Reverse Breakdown

• Critical E-field Avalanche breakdown
• Punch-through breakdown
• 3-D field crowding at real junctions
• Breakdown votage depends on
• Critical field
• Epitaxial layer doping
• Epitaxial layer thickness
• Edge-termination
• Upto 80 of ideal breakdown by Guard rings
• Upto 95 by Junction termination Extension

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SiC JBS diodes

• First used on Si by Williamovski and Baliga in
  1983-84
• High voltage Si JBS later demonstrated.
• Held and Dalquist realised SiC JBS diodes in 1998
• No advanced edge termination
• Later, very good JBS results achieved
• In 2004, J.Wu, L.Fursin, P.Alexandrov and J.Zhao
• 4308V blocking and 20.9m?.cm2 forward resistance
• 30µm drift layer and active area 1.4mm2

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Device Structure

• n-/n 4H-SiC epitaxial wafer
• 3 types of Devices- 3mm3mm, 4mm4mm 0.6mm0.6mm

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Fabrication Steps-1

• Wafer cutting, cleaning and alignment mark
  formation
• Device mesa is about 3000-4000A

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Fabrication steps-2

• P implantation
• Guard rings as well as PIN regions of MPS
• Post implantation annealing at 1550ºC for 30
  minutes

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Guard Ring Termination

• Many p implanted guard rings separated by
  schottky regions
• Designed to drop high voltage uniformly till edge
• Electric field minimised
• Right design of guard ring thickness and
  separation
• Photograph of guard rings under backlight

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Fabrication Steps-3

• Surface passivation by thermal oxidation and
  PECVD
• Window opening
• Backside metal ohmic contact (AlTi/Ni)

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Fabrication steps-4

• Substrate-side ohmic contact with
  Ti(800A)/TiW(2500A)
• Low schottky barrier height
• Overlay metals

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Photo- Masks
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Testing after Schottky contact
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Schottky metal Annealing

• Various annealing temperatures from 500ºC to
  600ºC for upto 1 hour tried.
• Annealing improves the Ti/SiC interface contact.
• Best improvement in reverse characteristics
• 550ºC for 20 in presence of inert gas Ar.
• Au (2.5um) is used as the overlay metal, which
  decreases the forward resistance by providing a
  larger area for the spreading current

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Testing after Schottky annealing
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After Au overlay
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Results

• 7 probes used after final overlay.
• 55A/cm2 at 1.5V and 170A/cm2 at 4V forward
• More than 1.2kV breakdown voltage.
• Yield is lower for bigger devices

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Summary

• Fabrication and DC testing were done
• SiC material quality bottleneck
• Switching test, high temperature test should be
  done
• Packaging would further improve forward
  performance

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Thank you!