Title: Scanning Tunneling Microscopy Controlled Continuous Lithography
1Scanning Tunneling Microscopy Controlled
Continuous Lithography Rob Sailer, Artur
Lutfurakhmanov, Iskander Akhatov, Doug
Schulz Center for Nanoscale Science and
Engineering and Department of Mechanical
Engineering, NDSU
Introduction The fabrication of nanoscale
features is becoming more important in todays
technology. As printed electronic features
become smaller the level of difficulty in
fabrication of devices increases significantly.
When fabrication must take place at the nanometer
of even angstrom level as is the case with tunnel
junctions, no lithography technology has
demonstrated the required capability with
Spintronics functional materials. The goal of
the current work is to fabricate simple
electronic junctions in the 100 nm range. Once
this has been demonstrated, materials with
Spintronics functionality, currently being
developed will be deposited in an effort to
fabricate Spintronics devices. Lithographic
techniques currently in practice consist of two
basic methods. Dip Pen nanolithography (DPN) is
a commercialized technology which is capable of
writing SAMs consisting of thiols on gold at sub
20 nm resolution. Continuous lithography has
demonstrated modification of polymers by solvent
dissolution with feature size on the 200 nm
range. The current lithography techniques are
severely limited by both materials that can be
deposited, conditions under which deposition can
take place, and control of feature size.
Additionally DPN is not a continuous technique
and the number of features which can be written
is limited. With respect to deposition materials
or inks no electronic material has been written
at this level.
- Path Forward
- Demonstrate STM scanning capability with well
characterized nanocapillary - Deposit model material and determine feature
size - Deposited electronic functional material
- Fabricate a simple electronic device such as a
diode - Fabricate a simple Spintronics device
- Institute Surface tension controlled
nanolithography tip to reduce feature size
This work supported by the NSF/EPSCoR Grant
0447679 and ND/EPSCoR Grant NDUS