Hardware%20Design%20of%20High%20Speed%20Switch%20Fabric%20IC

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Hardware Design of High Speed Switch Fabric IC
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Overall Architecture
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Features

• Supports protocol-independent switching. Data
  are encapsulated in switching packets across the
  fabric.
• Switching packet size is 64 bytes
• Supports 8x8 switch with each port up to
  2.563.2Gbps
• Supports scalable multichip switching

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Features

• 2.563.2Gbps I/O
• --CML IO driver
• --Embedded SERDES
• --Integrated CDR

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DeSerializer
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DeSerializer

• Converts the CML differential input to single bit
  input data through input CML buffer
• Converts the single bit input data at
  2.563.2Gbps rate into 16/20 bit data bus at
  160MHz clock rate
• Input reference clock 160MHz
• RX CML(clock multiplying unit) produces
  1.28-1.6GHz clock for data recovery from external
  160MHz clock

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DeSerializer

• Input reference clock 160MHz
• CDR(Clock Data Recovery) block produces
  1.28-1.6GHz clock for data recovery from external
  160MHz clock and input data
• Front End receiver use recovered clock to sample
  and de-multiplexing single input data to 4 bit
  data bus at 640MHz clock
• Use 4 to 16/20 DEMUX to produce 16/20 bit data
  bus at 160MHz

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DeSerializer

• Comma detector to detect comma word to align data
  byte boundary
• Use 8/10bit decoder to decode start of
  packet(SOP), destination port and data

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8x8 TDM switch
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8x8 TDM switch

• Performs the first stage load balanced traffic
  redistribution after the input FIFO queue
• Input to first stage switch is consecutive 64
  byte packet at each input port
• Outputs of first stage switch include data, data
  valid, destination port, and sequence ID

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8x8 TDM switch

• Performs the second stage Birkhoff-von-Neumann
  switch after the resequence and output buffer
  queue
• Input to second stage switch is distributive data
  from resequence and output buffer queue
• Outputs of second stage switch include data,
  start of packet, and destination port

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8x8 TDM switch

• Operates at 160MHz clock with clock period 6.2ns
• For 2.56Gbps(64 bytes/packet) 5Mpackets/s
• 200ns/packet operation time(time slot)32 cycles
  for 160MHz

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Serializer

• Performs 16/20b encoding function
• Parallel to serial conversion convert 20/16 bit
  data bus at 160MHz to single bit output at
  2.563.2Gbps
• Differential CML output

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PLL

• TXPLL to generate 160MHz clock for digital core
• TXPLL to generate reference 160MHz clock for
  synthesizing 1.281.6GHz clock for serializer
• RXPLL to generate 1.281.6GHz clock for CDR from
  external 160MHz clock

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Tasks

• PLLTR--PLL(TX and RX) design and Hspice
  simulation
• DESER--DeSerializer(CDR) design and Hspice
  simulation
• SWH-8x8 TDM switch design, synthesis, place and
  route, and verification
• CCODEC--Comma detect and 8/10b decoder, 8/10b
  encoder

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Tasks

• SERCMLSerializer and CML high speed IO buffer
  design and Hspice simulation
• APRDAnalog customized layout for DERSER
• APRS-- Analog customized layout for SER and
  driver
• Full chip integration and verification
• Architecture specs