Department of Electrical Engineering

1
RT-Level Vector Selection for Realistic Peak
Power Simulation
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
2007, 03, 13
Department of Electrical Engineering
National TsingHua University, HsinChu, Taiwan
2
Outline

• Introduction
• Vector Selection Methodology
• Mountain-based model
• Structure Analysis
• Peak Power Weight Calculation
• Waveform Composition and Vector Selection
• Experimental Results
• Conclusion

3
Introduction

• CMOS IC design with high transistor density
• High power dissipation
• Excessive instantaneous power dissipation (peak
  power)
• Signal integrity problems
• IR drop
• Electron-migration
• To design the power supply lines properly
• Accurate and efficient peak power estimation

4
Classification of Peak Power Estimation
Peak Power Estimation
Static Approaches
Dynamic Approaches
Upper Bound
Functional
Vector Generation
Lower Bound
Gate or Transistor Level
RT-Level
The Proposed
Realistic Reference
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Problem Definition

• Motivation
• Long power simulation time
• Large number of functional vectors
• Low-level power simulator
• Our aim
• Speed up the estimation process
• Select a small subset of vector pairs
• Among the entire functional patterns

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Outline

• Introduction
• Vector Selection Methodology
• Mountain-based model
• Structure Analysis
• Peak Power Weight Calculation
• Waveform Composition and Vector Selection
• Experimental Results
• Conclusion

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System Overview
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Mountain-Based Model

• The power contribution of each input is modeled
  as a mountain-shaped waveform.

Power Consumption
Circuit level
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Parameters

• To characterize the power waveform induced by a
  single transition occurring at a single input pin
  i
• Three parameters
• Maximum Structural Depth (Di)
• Peak Time (PTi)
• Peak Power Weight (Wi)

Peak power weight
Max. structural depth
Peak time
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Structure Analysis

• Decide Maximum Structural Depth Peak Time
• Maximum structural depth Di
• The potential time span of power consumption
• The maximum circuit level in the fanout gates
• Peak time PTi
• The peak power may occur
• The maximal number of gates could switch
  simultaneously

(Power Model of One Input Pin)
Max. structural depth
Peak time
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Example of Structure Analysis
x1
0
Max. of transitions
1,2
B
x2
A
0
1
D53
1
2,3
PT52
C
x3
D
0
0
H
x4
E
1,2
G
G
0
F
E
H
x5
F
1
D
D
E
2,3
H
G
0
Time Instance
1
2
3
x6
1,2
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Peak Power Weight Calculation

• Peak Power Weight (Wi)
• The relative amount of peak power induced by
  input i
• Two different calculation schemes
• Simulation-based scheme
• Structural scheme

(Power Model of One Input Pin)
Peak power weight
Max. structural depth
Peak time
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Simulation-Based Scheme

• Based on a previous proposed average power model
• Average power-weighting factor
• The influence of an input transition on total
  power consumption
• The area (relative energy) in our mountain model
• The calculation of peak power weight

(Area)
(Width)
(Height)
Ref M.Y. Sum, K.S. Chang, C.C. Weng, and S.Y.
Huang, ToggleFinder Accurate RTL Power
Estimation for Large Designs, Proc. of IEEE VLSI
Design, Automation and Test, pp.16-19, April 2005.
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Structural Scheme

• Based only on the structure information of the
  circuit
• Collect the loading capacitance at each gate
  output
• To reflect the realistic power
• Sum up the capacitances of those active gates at
  peak time

Assume output capacitance of A,B,C,D,E,F,G,H is
3,5,2,4,7,6,3,4 For input x5, at Peak Time
2 Peak power weight 4734 18
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Waveform Composition
x1
0
0
The relative amount of peak power induced by one
input vector pair
x2
1
1
Peak Power Metric
x3
1
0
23
19
x4
0
0
x5
1
0
x6
1
1
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Power Extrapolation and Evaluation
Extrapolation Phase
Evaluation Phase
RTL Simulation
Vector Selection
Cycle-Based Input Vector Pairs
Candidate Input Vector Pairs
Waveform Composition
Power Simulation
Worst-Case Peak Power
Peak Power Metrics
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Outline

• Introduction
• Vector Selection Methodology
• Experimental Results
• Conclusion

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Experimental Environment

• Simulation tools
• RT-level gate-level simulator Verilog-XL
• Gate-level power simulator PrimePower
• Transistor-level power simulator NanoSim
• Test cases

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Accuracy Metrics Definitions

• Number of Matches
• True rank In terms of the peak power value
  estimated by low-level power simulation results
• Predicted rank In terms of the peak power
  metrics
• Match A candidate vector pair is called a match
  if its true rank is smaller than number of
  selected vectors
• Peak Power Match Order
• The predicted rank of the worst-case vector pair

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Accuracy Comparison
Reference The simulation results obtained by
Nanosim or PrimePower
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CPU Time Comparison
Results obtained by running PrimePower
Full Simulation Time the power simulation time
for the entire vector set
Total Time the modeling time, RT-level
simulation, waveform composition, power
simulation time
Speedup (Full Simulation Time) / (Total Time)
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Outline

• Introduction
• Vector Selection Methodology
• Experimental Results
• Conclusion

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Conclusion

• Vector Selection Methodology
• Mountain-Based Power Model
• Waveform Composition
• Peak Power Estimation Flow
• Quick vector selection process in RT level
• Accurate power simulation in low level
• Large set of functional patterns affordable
• Only 1 of total patterns are selected
• Speedup more than 40X compared with quick-spice
  simulator
• Retaining the accuracy of low-level power
  simulator