J. D. Plummer, M. D. Deal, P. B. Peter

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J. D. Plummer, M. D. Deal, P. B. Peter
Silicon VLSI Technology

• Chapter 2
• CMOS Technology

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MOS Device Physics

• Current will be Minority Carriers of well under
  Gate!
• Quiescent State Gate is zero or reverse polarity
  (voltage) of well (- for p-type and for
  n-type.) This repels/depletes silicon below gate
  (between S and D) of any minority carriers.
• Conducting State Gate is same as well ( for
  p-type and for n-type wells).
• Gate pulls minority carriers of well from
  substrate to thin layer (5nm) connecting Source
  and Drain with their majority carriers (Majority
  carriers of S/D Minority carries of well!)
• Forward bias of Source/Gate injects majority
  carriers into thin layer.
• Reverse Bias of Gate/Drain creates field that
  pulls majority carriers into Drain.

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CMOS Circuit Diagram
S D
S D
S D
D S
D S
D S
NOR Only HIGH if both IN1 and IN2 are LOW.
Inverter
NOR
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Typical Logic Cell
2-input NAND gate
S D
S D
A
B
D S
Out
D S
GND
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Dual-Well Trench-Isolated CMOS
gate oxide
field oxide
Al (Cu)
SiO2
TiSi2
tungsten
SiO2
p well
n well
p--epi
p
n
P
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Final CMOS Planar Device
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Top View of CMOS Inverter
IN
OUT
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Top View of CMOS Inverter
Slide with 90o Rotation
IN
OUT
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P-Well Mask
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Poly-Silicon Connector Mask
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P Source/Drain Mask
? Self-Aligned Gate ?
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N Source/Drain Mask
? Self-Aligned Gate ?
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Source/Drain Contacts Mask

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Local Interconnect Metal
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Initial Si Substrate Preparation
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CMOS Mask 1
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CMOS Grow Gate Oxide
Note Growing with O2 gas limits growth to
maximum of 5nm. Growing in H2O allows H to form
hydroxals, weakening the glass, and it can
continue to grow oxide up to 1um. For thick
glass, need to end by baking in vacuum to drive
the H out of the oxide film.
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Ion Implant n-well
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P Implant for p-MOS device
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Thermal Drive-In of Wells
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Threshold Adjust Implantation
Threshold Adjust Implantation (p)
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Threshold Adjust for p-MOS Device
Threshold Adjust Implantation (n) (increases
mobility)
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Deposit Final Gate Oxide
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Polysilicon Connector of Gates
Implant dopes Polysilicon increasing conductivity
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Gate Protection Layer
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Mask Implant of NMOS Device
Uses self-aligned Gate implant process.
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Boron Implant for PMOS
Uses self-aligned Gate implant process.
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SiO2 Layer Added
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Etch of Gate Sidewall Spacers
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As Implant for NMOS Regions
Sidewall Spacers keep heavy implant dopants
away from directly under Gate contact.
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B Implant for PMOS Regions
Sidewall Spacers keep heavy implant dopants
away from directly under Gate contact.
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Drive-In Anneal to Remove Damage
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Oxide Etch for Final Contacts
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Titanium Layer for Contacts
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TiSi2 formed for Ohmic Contact
TiSi2 formed where Ti touches silicon
TiN formed from N2 gas
Two separate Reactions occur simultaneously ! Ti
Si ? TiSi2 Ti N ? TiN BOTH TiSi2 and
TiN are CONDUCTORS !
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Etch of TiN Forming Interconnects
TiN etch does NOT effect TiSi2 Local
Interconnects TiN (10O/?), TiSi2(1 O/?)
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Final SiO2 Layer for Planarization
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Planarization Polishing the Wafers
From Smithsonian, 2000
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Chemical/Mechanical Polish
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Final Contact Holes (Vias)
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Metallic Deposition for Vias
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CMP Repeated for Planarization
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Back-End of the Line Metal
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CMOS Process Overview

• 16 Masks
• 103 Process Steps
• Typical time for completion 4 months

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New Concepts in this Lecture

• Complex CMOS NAND and NOR Circuits (2-4)
• Masks Identifying CMOS Processing Masks (6-11)
• Thermal Oxides Different SiO2 growth using O2 vs.
  H2O gases (13)
• Sidewall Spacers Used for both electrical
  isolation and to mask 2nd source/drain implant
  (27,28)