CSE 242A Integrated Circuit Layout Automation

1
CSE 242A Integrated Circuit Layout Automation

• Lecture Floorplanning
• Winter 2009
• Chung-Kuan Cheng

2
Outlines

• Introduction
• Representations and Approaches
• Constraint Graph
• Triangulation
• Tuttes Duality
• Slicing Flooplanning
• Nonslicing ...
• Block Handling
• Research Directions

3
Introduction

• Input
• A set of blocks with constraints on
• area, shapes, relative positions,
• Constraints on chip area and aspect ratio,
• Netlist.
• Output
• Shapes, Locations, Pin positions of the blocks
• Objective Functions
• Performance, chip area, and wire length

4
Representations

• Constraint Graph
• Theorem A V or H constraint graph is planar and
  acyclic.

5
Constraint Graph Generation
Edges O(n2), O(n)
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Constraint Graph Generation

• Scan from left to right at cur_x
• Update scaline list of blocks crossing
  scanline.
• For blocks T strating at cur_x
• Insert T into scanline list
• R-gtT-gtS
• Generate edges
• R-gtT and T-gtS
• End

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Constraint Graph Generation 2

• Scan from left to right at cur_x
• Update scanline list of blocks crossing
  scanline.
• For blocks T starting at cur_x
• Insert T into scanline list R-gtT-gtS
• Generate listT.topR, R.botT, T.botS,
  S.topT
• End
• For block T ending at cur_x
• if T.top is list in scanline, generate edge
  T.top-gtT
• if T.bot is list in scanline, generate edge
  T-gtT.bot
• End
• End

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Floorplan Triangulation

• Floorplan with dead space

• Floorplan with zero dead space

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Triangulation

• For floorplan with zero dead space, H V
  constraint graphs are dual.

• H V
• Every face is a triangle
• All internal nodes have a degree gt 4
• All cycles that are not faces have length gt 4

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Triangulation 2

• Node oriented vs edge oriented constraint graph

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1
b
2
a
c
e
3
d
4
f
g
5
10
6
7
11
Tuttes Duality
s
s
c
a
c
a
d
b
b
d
t
t
12
Slicing Floorplan General Flow
V
H
H
V
H
1
2
5
4
3
6
Nonslicing
13
Routing Region Definition Ordering
Straight Channel
L Shaped
b
b
1
a
a
1
2
3
c
2
c
Feasible Order
Non-Feasible Order
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Polish Expression
v
3
H
1
6
V
4
H
V
H
7
2
5
4
3
6
1
5
7
2
2 1 H 5 7 V 4 3 H 6 V H V
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• Given n components, there are n-1 operators
• Polish Exp has 2n-1 length
• Polish Exp is legal iff
• operators lt comps 1
• For any prefix substring
• 2 1 H5 7 V 4 3 H 6 V H V
• 2 1 5 H 7 V 4 3 H 6 V H V
• 2 1 5 H V H V 7 4 3 6 H V

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Redundancy of Polish Exp
3
1
2
V
V
V
V
1
2
3
2
3
1
1 2 3 V V
1 2 V 3 V
No consecutive operators of the same type
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Neighborhood Structure

• OP. Chain VHVHV or HVHV
• 2 3 V 1 4 H 5 V 6 H V V
• M1 Swap adjacent components
• M2 Complement a chain
• M3 Move an operator under the prefix constraint
  of operators lt comps 1

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5
3
1 2 V 3 H4 V 5 H
4
1
2
5
5
4
4
3
1 2 V 4 H 3 V 5 H
1 2 V 4 3 5 H V H
3
1
2
1
2
3
5
5
4
3
4
1 2 H 4 3 5 H V H
1 2 V 4 H 3 5 V H
2
1
2
1
3
2
5
3
5
4
1 2 V 4 3 H 5 V H
1 2 H 4 3 5 V H V
1
1
2
4
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The choices of macro cell
H
3
4
V
2
H
1
2
3
4
1
Hi
Hj
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21
Hierarchy Floorplan
K2
K3
K4
22
a
b
d
c
e
a3
a1
b1
b2
a4
a2
a6
b4
b5
a5
b3
a11
a12
a14
a13
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Sequence Pair
b
a
b
a
b
b
a
a
Eg. c a e b d a b c d e
c
e
combinations
a
b
d
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Grid System Interpretation
5
e
4
d
a
r
3
c
x
2
b
1
a
l
b
1
2
3
4
5
25
Bounded-Sliceline Grid

• Perturbation move a component to another room

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BSG Adjacency Graphs

• Theorem nxn grid contains the complete solution
  space for n components

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Twin Binary Trees

• Definition of Twin Binary Trees
• Transformations between Floorplan and Twin Binary
  Trees

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Twin Binary Trees
T
T
T
T
2700
1800
900
00
C-neighbor 00 T-junction, block on right
2700 T-junction, block on top
C--neighbor 900 T-junction, block on top
1800 T-junction, block on left
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Twin Binary Trees
?(?1)11001
?(?2)00110
order(t1)order(t2)ABCDFE
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Twin Binary Trees and Mosaic Floorplan
Twin Binary Tree ? Mosaic Floorplan ? one to one
mapping Transformation between twin binary trees
and mosaic floorplan takes linear
complexity twin binary trees Baxter number
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Corner Block List

• Corner Block List ? Mosaic Floorplan
• A permutation and two 0-1 lists
• e.g. S(fcegbad), L(001100), T(001010010)

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Corner Block List

• S(fcegbad), L(001100),
• T(001010010)
• S is the reversed sequence of removed blocks
• Li is the removing direction of block i
• Number of 0s before ith 1 in T is the number
  of blocks covered by Si when it is removed

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Corner Block List

• Redundancy (L and T are not independent)
• Solution space size O(n!23n-3/n1.5)
• Can be reduced to O(n!23n-3/n4), no redundancy

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Floorplan Optimization Flow

• Simulated annealing (SA) in the representation
  solution space

s s0 e E(s) //
Initial state, energy. sb s eb e
// Initial "best" solution k
0 // Energy
evaluation count. while k lt kmax and e gt emax
// While time remains not good
enough sn neighbour(s)
// Pick some neighbour. en E(sn)
// Compute its energy.
if en lt eb then //
Is this a new best? sb sn eb en
// Yes, save it. if P(e, en,
temp(k/kmax)) gt random() then // Should we
move to it? s sn e en
// Yes, change state. k k 1
// One more
evaluation done return sb
// Return the

• E() is the objective function
• neighbour(s) comes from perturbation on s