A Petri Net Model for HardwareSoftware Codesign by

1
A Petri Net Model for Hardware/Software
Codesignby
Paulo Maciel prmm_at_di.ufpe.br Advisor
Edna Barros Co-advisor Wolfgang Rosenstiel
Departamento de Informática
Universidade de Pernambuco - Brazil

2
A Petri Net Model for Hardware/Software Codesign

• Outline
• Introduction
• Hardware/Software Codesign Problem
• Design Activities
• Related Works
• PISH Methodology an Overview
• An Introduction to Petri Nets
• The Occam - Timed Petri Net Translation Method
• System Analysis
• Communication Cost
• Mutual Exclusion

3
A Petri Net Model for Hardware/Software Codesign

• OUTLINE
• Software Model
• Hardware Model
• Time Analysis
• - Structural Approach
• Reachability aApproach
• Reductions
• Clock Period Estimation
• Load Balancing
• Hardware Area
• High-Level Control Area Estimation
• Local Controller Area Estimation
• Data-Path Area Estimation
• Structural Based Method
• Reachability Based Method
• Results
• Conclusion
• Further Works

4
A Petri Net Model for Hardware/Software Codesign

• Results
• Conclusion
• Further Works

5
A Petri Net Model for Hardware/Software Codesign

• Hardware/Software Codesign Problem
• The hardware/software codesign problem
  consists in implementing a given system
  functionality in a set of interconnected hardware
  and software components, taking into account
  design constraints.

• Behavioral description

Partitioner system
Hw
Proc.
Proc.
Hw
...
...
n
1
m
1
6
A Petri Net Model for Hardware/Software Codesign

• Some Important Tasks and Policies
• qualitative analysis/verification
• fast partitioning algorithm
• quality metrics estimation/quantitative
• analysis
• prototyping
• reduction of the required time-to-test
• fast design exploration
• re-use of previous designs

• Some Important Concerns
• cost
• timing constraints
• area
• power consumption
• time-to-market

7
General Design Activities of a Hardware/Software
Codesign
8
General Design Activities of a Hardware/Software
Codesign

• Quantitative Analysis
• Quantitative analysis concerns metrics
  computation and estimations.
• Enable designers to evaluate design quality
  comparing estimates with constraints of a given
  metrics.
• Enable designers to explore design alternatives
  by providing a quick feedback for design decision.

9
General Design Activities of a Hardware/Software
Codesign

• Quantitative Analysis
• This is an important task in a hardware/software
  codesign system, since performance and costs of
  products are highly dependents on partitioning
• Hardware/software partitioners are ruled by
  metrics, hence quality estimation algorithm are
  essential for implementing products with intended
  needs and constraints.
• Accuracy ? Speed
• Fidelity

10
Main Goal

• Provide an indepent of the language intermediate
  formal model which allows for qualitative,
  quantitative analysis and simulation.
• Provide a set of methods of computing metrics for
  
• hardware/software codesign.

11
Related Works

• Vulcan II
• Stanford University
• (De Micheli et al.)
• HardwareC
• Data Flow Graph

• Performance of hardware and software are
  estimated from the flow graph and basic delays of
  operators
• The size of hardware is estimated from size
  attribute of an operation. It does not estimate
  control area.
• Software size program and data size

12
Related Works

• COSYMA
• Braunschweig University
• (De Ernst et al.)
• C
• Data Flow Graph

• Software perfomance is estimated from the object
  code generated by the compiler and considering
  simulation.
• Hardware execution time is estimated with a list
  scheduler.
• Communication cost is provided in terms of delay.
• The maximum size of hardware is provided by the
  designer.

13
Related Works

• PURE
• Linköping University
• (P. Eles et al.)
• XVHDL
• Petri Nets

• The intermediate model is used for cosimulation
  in order to collect data and statistics about
  data usage and control flow choices.
• Metrics are explicitly provided by the designers
• Qualitative analysis is not considered

14
Related Works

• LYCOS
• Technical University of Denmark
• (J. Madsen et al.)
• C, VHDL
• CDFG

• Software execution time is estimated from the
  flow graph and takes into account the processor
  technology file
• Hardware execution time only consider the data
  flow graph, so far.
• No formal method has been provided for computing
  control area, resource sharing register area.
• Communication is fixed to memory mapped I/O.

15
Related Works

• SpecSyn
• University of California
• - Irvine -
• (D. Gajski et al.)
• SpecChart

• Metrics estimation is language dependent.
• Metrics for estimating connectivity, shared
  hardware and communication.
• Methods of computing hardware and software area
• No algorithm of estimating resource sharing and
  mutual exclusion.

16
Related Works

• COSMOS
• TIMA - France
• (A. Jerraya et al.)
• SDL, VHDL
• EFSM and RPC

• Supports description levels ranging from RTL to
  system-level.
• Cosimulation allows validation of a virtual
  prototype.
• The system lacks of method for performing
  estimation in order to guide the process.

17
OCCAM description

M E T H O D O L O G Y
translation OCCAM-PN
qualitative analysis
splitting
classification
Petri Net
quantitative analysis time analysis communicati
on cost load balance cost precedence
relation degree functional similarity area
estimation number of processor estimation
P I S H
choosing an alternative
initial allocation
clustering
joining
architecture generator
yes
no
another alternative
implementation
18
Splitting Phase

• The behavioral description is split into a set of
  concurrent processes
• L6 - PAR(p1,p2,...,pm) PAR(p1,PAR(p2,...,pm))
• L10 - PAR(SEQ(ch?x,p),SEQ(ch!e,q))
  SEQ(xe,PAR(p,q))

19
Classification

• A set of implementation alternatives is generated
  considering parallelism degree and pipelining
• PAR i0 for 2
• PAR j0 for 2
• bije1

• PAR i0 for 2
• SEQ i0 for 2
• bije1
• SEQ i0 for 2
• PAR i0 for 2
• bije1
• SEQ i0 for 2
• SEQ j0 for 2
• bije1

20
Implementation Choice

• Manual
• Automatic - a balanced implementation of
  processes is chosen considering the parallelism
  degree

21
Initial Allocation

• The best suited simple processes to software
  implementation are allocated to each processor in
  the architecture
• Criteria - interprocessor communication
• - precedence relation
• - load balance

22
Clustering (Hw/Sw Partitioning)

• The other simple processes can either migrate to
  software components or be implemented in hardware
• Criteria - functional similarity
• - interprocessor communication
• - precedence relation
• - load balance
• - area-delay cost function
  
• minimization
  

23
Joining Phase

• Based on the clustering result, processes in each
  cluster are joined using transformation rules

24
Qualitative Analysis

• Qualitative analysis is carried out by
  cooperative use of structural and reachability
  methods, and reduction rules

25
Quantitative Analysis

• time analysis / delay estimation
• communication cost
• load balance
• precedence relation
• functional similarity
• area estimation
• estimation of number of processors
• clock period estimation of hardware

26
Timed Petri Net

• TPN (P,T,I,O,M0 ,D)
• P - Places N
• T - Transitions N
• I - Input Arcs P ? T N
• O - Output Arcs P ?????????
• D - Duration T R

p0
p3
t0
t4
p6
t3
t6
p1
p4

t1
t5
p2
p5
27
OCCAM Description Language

• Example
• INT a,b,c
• SEQ
• PAR
• aa1
• bb1
• cd4

• P xe ch ? x ch ! x SKIP STOP
• SEQ PAR
• IF ALT WHILE
• BOX CON
• VAR CHAN

28
T r a n s l a t i o n
O C C A M - T P N
29
OCCAM - Timed Petri Net Translation

• Assignment
• control and data-flow
• Example
• xy1

30
OCCAM - Timed Petri Net Translation

• Communication
• Synchronous message passing

31
OCCAM - Timed Petri Net Translation

• Parallel Combiner
• fork and join
• Example
• INT a,b,x,y
• PAR
• af(x)
• bg(y)

p0
t0
p1
p3
t1
t2
p4
p2
t3
p5
32

• INT CHAN Ch1,Ch2
• PAR
• INT a,b Process P1
• SEQ
• ab1
• IF alt3
• aa1
• agt3
• aa2
• Ch1 ! a
• bb1
• INT c,d Process P2
• SEQ
• d0
• Ch2 ? c
• dc1
• Ch1 ? c
• ddc
• Ch2 ! d

T r a n s l a t i o n
O C C A M - T P N
33
OCCAM - Timed Petri Net Translation

34
System Analysis
Qualitative Analysis

• Behavioral Properties
• Reachability
• Coverability
• Deadlock freedom
• Liveness
• Reversibility
• Boundedness
• Safeness
• Persistence
• Fairness

• Structural Properties
• Repetitiveness
• Consistence
• Structural Boundedness
• Conservation

35
System Analysis

• Complexity ? Precision
• Cooperative use of these methods
• Use of Petri net sub-classes
• Possible sequence of steps
• closure
• reductions
• structural methods
• reachability based methods

Analysis Approaches

• Behavioral Methods
• Structural Methods
• Reductions

36
Petri Net Sub-Classes
PN
SIMPLE NET FC
MG SM

37
Quantitative Analysis

• Independent of the architecture metrics
• Communication cost
• Mutual exclusion degree
• Precedence relation degree
• Resource sharing (structural)

• Dependent of the architecture metrics
• Timing analysis
• Load balance
• Clock period estimation
• Area estimation
• Resource sharing (allocation)

38
Communication Cost

• For each process
• NC(pri ) nc(pri ) ? max(xk (pri )j) , if
  tj ? TCA ? Xk
• 
  0,
  otherwise
• CC(pri) NC(pri ) x NBc
• NCC(pri) CC(pri) (Global
  Normalization)
• CC(D)
• L CC(pri) CC(pri) (Local
  Normalization)
• ??p ?PCC(prj)

39
Communication Cost

• For pair of processes
• NC(pri, prj ) nc(pri, prj ) ? min(nc (pri ),
  nc (prj)) , if tk ? TCA
• 
  0,
  otherwise
• CC(pri , prj ) NC(pri, prj ) x NBc
• NCC(pri , prj) CC(pri , prj )
• CC(D)
• LCC(pri , prj) CC(pri , prj )
• CC(pri ) CC(
  prj )- CC(pri , prj )

40
Communication Cost
41
Communication Cost
42
Mutual Exclusion

• Causal Precedence Relation Resource Sharing

43
Mutual Exclusion Degree

• Local Mutual Exclusion Degree between Processes

44
Mutual Exclusion Degree

• Local Mutual Exclusion Degree

45

• INT CHAN Ch1,Ch2
• PAR
• INT a,b Process P1
• SEQ
• ab1
• IF alt3
• aa1
• agt3
• aa2
• Ch1 ! a
• bb1
• INT c,d Process P2
• SEQ
• d0
• Ch2 ? c
• dc1
• Ch1 ? c
• ddc
• Ch2 ! d

M u t u a l E x c l u s i o n
Degree
46
Example

• Process P1
• Places p1,p4,p7,p8,p11,p14,p16
• Transitions t1,t4,t5,t7,t8,t11,t12
• Process P2
• Places p2,p5,p9,p12,p15,p18,p19
• Transitions t2,t6,t9,t11,t13,t14
• Process P3
• Placesp3,p6,p10,p13,p19,p20
• Transitions t3,t6,t10,t14,t15

47
Example

• Sp0p0,p1,p4,p7,p8,p11,p14,p16,p21
• Sp1p0,p1,p4,p7,p8,p11,p15,p17,p18,p21
• Sp2p0,p1,p4,p7,p8,p11,p15,p17,p19,p20,p21
• Sp3p0,p2,p5,p9,p12,p15,p17,p18,p21
• Sp4p0,p2,p5,p9,p12,p14,p16,p21
• Sp5p0,p2,p5,p9,p12,p15,p17,p19,p20,p21
• SP6p0,p2,p5,p10,p13,p18,p21
• Sp7p0,p2,p5,p10,p13,p19,p20,p21
• SP8p0,p3,p6,p10,p13,p19,p20,p21
• Sp9p0,p3,p6,p9,p12,p14,p16,p21
• Sp10p0,p3,p6,p9,p12,p15,p17,p18,p21
• Sp11p0,p3,p6,p9,,p12,,p15,p17,p19,p20,p21

48
Example

• LME(p1,p2) 23/49 0.4694
• LME(p1,p3) 14/42 0.3333
• LME(p2,p3) 30/42 0.7143

49
Mutual Exclusion Degree
50
Mutual Exclusion Degree
51
Software Model

• Sequential execution
• Technology File
• Instruction size
• Instruction delay
• INMOS technology file

52
Hardware Model

• Technology File
• basic units
• delay
• size
• FU
• operation delays
• FU size

• Operations in na expression
• are sequentialy executed

53
Clock Estimation

• Minimal Clock Period
• Tclk ?mind(opj)?,
• Maximal Clock Period
• Tclk ?maxd(opj)?,
• Average Clock Period
• Tclk ??opjd(opj)? NOP(opj, ti)/ ? ti NOP(opj,
  ti) ?
• ? opj ?OPS, ?ti ?Tal

INT a,b,c,d SEQ aa1 b b3
cc?3 dd1
Tclk35
35 35 51 35
35 35
54
Clock Estimation

• INT a,b,c,d,e
• PAR
• SEQ
• aab
• IF a lt 3
• a(a-b)c
• a gt 3
• a(ab) (ac)
• dde

Tclkmin Tclkmax
Tclkave Ahhls 188 84
116 CT 351 582
416 MT 297 485 364 LMT
324 533.5 390
55
Time Analysis

• Reachability method path finder algorithm
• Structural methods
• Reductions

56
Timing Estimation

• Hardware
• Transition durations
• operation delays
• Structural method
• CT, MT, LMT
• (no resource constraint)
• Reachability method
• Allocation INA (MT)
• (resource constraint)

• Software
• Transition durations
• operation delays assignment delay
• Reachability method
• Allocation INA (MT)
• (resource constraint)

reachability based methods may only be used
for bounded systems
57
Timing Estimation

• Transition Duration

• Ds (e) Ds (e) Ds (e)
• Dh (e) Dh (e)

ex
rw
op
op
ex

D (op ) x op
??
oph
if ehardware
,
i
i
D (e)
op
e
?
?
i
op
D (op ) x op
??
,
ops
if esoftware
i
i
op
e
?
?
i
58
Timing Estimation

• Structural Method
• Model should be - safe
• - strongly
  connected
• - covered by
  place-invariant
• Model shoud have - start place initially
  
• marked
• - final place
• - no shared
  place

59
Timing Estimation

• Structural Method
• Metrics - minimal time
• - critical path time
• - likely minimal time

60
Structural Method
p
0
t
1,2
0
p
p
1
p
3
2
2,3
t
t
2,3
5,8
t
2,3
t
1
2
10
p
8
p
p
p
4
p
5
12
11
11,12
0,0
11,12
t
9
1,2
t
t
3,4
t
t
t
3
6
16
9
11
1,2
p
13
p
p
p
p
10
p
19
20
6
8
13
1,2
t
t
t
1,2
t
t
17
4
18
7
3,5
15
5,7
5,7
p
p
p
14
15
7
t
t
2,3
p
12
1,2
5
p
1,2
16
17
t
p
14
18
61
Structural Method

• T-minimum invariants

st
t ,t ,t ,t ,t ,t ,t ,t ,t ,t ,t ,t
,t
0
2
6
7
8
9
0
10
11
12
13
14
15
17
st
t ,t ,t ,t ,t ,t ,t ,t ,t ,t ,t ,t
,t
1
0
2
6
7
8
9
10
11
12
13
14
16
18
62
Structural Method
p
0
t
1,2
0
p
p
1
p
3
2
t
2,3
5,8
t
2,3
t
2
10
8
p
p
p
p
5
12
11
11,12
0,0
11,12
9
t
t
3,4
t
t
t
6
16
9
11
1,2
p
13
p
p
p
10
p
19
20
8
13
1,2
t
t
t
t
17
18
7
3,5
15
5,7
5,7
p
p
14
15
t
2,3
p
12
p
1,2
16
17
t
p
14
18
63
Structural Method

• P-minimum invariants
• sp p ,p ,p ,p ,p ,p
• sp p ,p ,p ,p ,p ,p ,p ,p
• sp p ,p ,p ,p ,p
• sp p ,p ,p ,p ,p
• sp p ,p ,p ,p ,p ,p
• sp p ,p ,p ,p ,p ,p ,p

0
1
1
5
8
16
18
18
2
3
12
15
17
19
20
0
0
1
5
18
3
10
18
2
4
10
9
0
0
5
8
16
18
2
9
18
3
11
13
14
17
0
64
Structural Method

• Transition paths
• sn t ,t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t ,t ,t

1
2
6
7
0
13
14
2
0
10
11
12
13
14
16
17
18
2
3
6
0
13
14
4
6
8
0
13
14
5
6
7
8
0
13
14
6
9
0
10
12
13
14
15
65
Structural Method

• Path decomposition
• sn t ,t ,t ,t ,t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t ,t ,t
• sn t ,t ,t ,t ,t ,t ,t

2
0
10
11
12
13
14
16
17
18
21
0
10
11
12
13
14
17
22
0
10
12
13
14
16
18
66
Structural Method

• Critical path time
• CT(N) max T(sn ),T(sn ),T(sn ),T(sn ),
• T(sn ),T(sn ),T(sn ) 22
• Minimal time
• MT(N) max T(sn ),min T(sn ),
• T(sn ),T(sn ),T(sn ),T(sn
  ),
• T(sn ) 20

1
21
22
3
4
5
6
1
21
22
3
4
5
6
67
StructuralMethod

• Likely minimal time
• ????
• lmt(sn ) ??d(t ) x pev(t )
• ?
• LMT(N) max lmt(sn ),lmt(sn ),lmt(sn ),
• lmt(sn ),lmt(sn ),lmt(sn
  ) 21
• MTina MT CT LMT
• 20 20 22 21

j
j
k
?
?
t
sn
k
j
1
2
3
4
5
6
68
Timing Estimation

• Reachability Based Method

69
Timing Estimation

• Reachability Based Method

MT 10 ns
70
Load Balance

• Load (p ,P ) NC(p ,P )
• Nload (p ,P ) Load (p ,P )/Load (D,P )
• LLB (p ,P p ,P )

k
i
i
k
k
k
k
i
i
Load (p ,P ) - Load (p ,P )
k
i
j
l
j
k
i
l
Load (p ,P ) Load (p ,P )
i
j
k
l
71
M u t u a l E x c l u s i o n

• Convolution Function
• CHAN OF INT P1.P4, P2.P4, P4.P3
• CHAN OF 5 INT P3.P4
• PAR
• INT c
  Process P1
• SEQ i0 FOR 2
• IF (xigt0 cxi, xilt 0
  cxi/2)
• p1.p4 ! c
• INT d
  Process P2
• SEQ i0 FOR 2
• IF(xigt0 dxi1, xilt0
  dxi1/2)
• p2.p4 ! d
• INT w
  Process P3
• SEQ i0 FOR 2
• p4.p3 ? w
• PAR j0 FOR 4
• ejx5(i/(j((j1)/(i1
  ))))(j-i)w
• p3.p4 ! e
• INT c,d
  Process P4

Degree
72
Load Balance
Processes LLB
p p p p p p p p p p p p
0
2
1
0.8852
3
1
0.9427
1
4
0.8852
3
2
2
4
0.9427
0.3475
3
4
73
Area Estimation

• Hardware process area
• AH(prk) AHop(prk) AHrw(prk)
• Am(prk) AHlc(prk)
• AHhlc(prk)
• AHop(prk) - Functional unit area
• AHrw(prk) - Variable area
• Am(prk) - Multiplexer area
• AHlc(prk) - Local control area
• AHhlc(prk) - High-level control area

• Hardware model

Data path
Local control
High level control
Local control
Data path
74
Area Estimation

• High-level control

• Hardware model

fne
a
c
c
Q
D
Data path
a
Local control
clk
High level control
fpe
fne
a
c
c
Q
Local control
Data path
D
a
clk
fpe
a
c
a
c
b
d
b
d
fne fne
fpe fpe
75
Area Estimation

• Place Implementation

• QN QN1 QN1 QN1 QN1
• a0, fne0 a0, fne1 a1, fne0 a1,
  fne1
• 0 0 0
  1 1
• 1 1 0
  1 1

fne
a
c
c
Q
D
a
clk
fpe
a fne
00 01 11 10
0 2 6 4 1
3 7 5
0 0 1 1 1 0
1 1
0 1
Q
D a Q fne
76
Area Estimation

• High-level control area
• AHhlc(prk) AHpl(prk)
• AHtr (prk)

• Place area
• AHpl(pj) DFA AA x O(pj)
• OA x I(pj)
• AHpl(prk) ??pj ? P Ahpl(pj)

77
Area Estimation

• Transition area
• AHtr (prk) Ait(tj) Aot(tj) , d
  (tj) ? Tclk
• Ait(tj) Aot(tj) ,
  d (tj) gt Tclk
• NP ? (FDAAOAA)
• Ait(tj) AA(tj) x (I(tj) - 1)

• High-level control area
• AHhlc(prk) AHpl(prk) AHtr (prk)

, I(tj) ? 0
0 , I(tj)0
AA(tj) x (O(tj)-1)
, I(tj) ? 0
Aot(tj)
0 , I(tj)0
78
Area Estimation

• Local controller area

• Hardware model

inputs
Address lines
ROM
State register
Data path
Local control
High level control
outputs
Control lines
AHls(prk)((??ej ? prkVS(ej) ??op_type ?
OPSFUN(prk,op_type)MN(prk)) x (??ej ? prk ??opi
? ej opi x Doph(opi)) (log2 ??ej ? prk ??opi
? ej opi x Doph(opi))) x AHb
Local control
Data path
79
Area Estimation

• Data-path model

r1
r2
r3
r4
Data path
Local control
MUX
High level control
MUX
MUX
Local control
Data path

80
Area Estimation

• Data-path model
• Variable area
• Multiplexer area
• Functional unit area
• Functional unit area
• AHop(prk) ??op_type ? OPS
• FUN(prk,op_type) x
  AHop_type

FUN(prk,op_type) STPS STPS ? UTPS, where
UTPS ?i TPSi TS(prk, op_type) ? STPS, ? X ?
STPS such that TS(prk, op_type) ? X . TPSi -
Transition path set UTPS - Universal transition
path set TS(prk, op_type) - Transition set of
type op_type. STPS - The
smallest transition path set that
contaains TS. FUN (prk, op_type) - Number of
functional units
81
Area Estimation - Structural Analysis -

• P-minimum invariant supports
• sp0p0,p1,p3,p5,p6
• sp1p0,p2,p4,p5,p6
• Transition paths
• Tp0t0, t1, t3, t4
• Tp1t0, t2, t3, t4
• TS()t1, t2, t4 ? FUN() 2

t0
bb1
aa1
t1 t2
t5
t3
cd4
t4
82
Functional Unit Estimation

• Reachability Based Method

83
Functional Unit Estimation

84
Functional Unit Estimation

• Reachability Based Method

85
Functional Unit Estimation

86
Functional Unit Estimation

• Example C

87
Functional Unit Estimation

• Estimation Results

88
Area Estimation

• CHAN OF INT value, change
• CHAN OF BOOL inc,ssd,stck,gsd,ref
• INT x,y
• BOOL incv,ssdv,stckv,gsdv,refv
• SEQ
• x0
• WHILE ssdvFALSE
• SEQ
• inc ? Incv
• WHILE incv FALSE
  inc ? Incv
• value ? y
• xxy
• ssd ? ssdv
• stck ? stckv
• IF
• stckv FALSE
• ref ! TRUE
• stckv TRUE
• SEQ

• IF
• x lt 0
• ref ! TRUE
• x gt 0
• SEQ
• change ! X
• gsd ! TRUE
• Units Estimated PN MOORE
• FU 144 144
  144
• Reg 96 96
  96
• Mux 64 48
  48
• Control 128 150 150
• AH 432 429
  478

89
Results

• Vending Machine

• Process AHw(gc) ASw(gc) DHw(ns) DSw(ns)
• P1 983 360 2295 26250
• P2 1109 504 1683 18900
• P3 702 444 918 33750
• P4 4504 256 1224 14650
• P5 5413 532 1683 18000
• P6 366 220 918 22950
• P7 156 72 765 38250
• Table Area and delay values

90
Results

• Vending Machine

• Local comm.. Normal comm... Mutual Exclusion
• P1,P2 0 0 0.184
• P1,P3 0.359 0.333 0.824
• P1,P4 0 0 0.856
• P1,P5 0 0 0.913
• P1,P6 0 0 0.807
• P1,P7 0 0 0.794
• P2,P3 0.265 0.214 0.829
• P2,P4 0 0 0.864
• P2,P5 0 0 0.921
• P2,P6 0 0 0.814
• P2,P7 0 0 0.800
• P3,P4 0 0 0.779
• P3,P5 0 0 0.831
• P3,P6 0 0 0.735
• P3,P7 0.069 0.048 0.786
• P4,P5 0 0 0.882
• P4,P6 0.292 0.167 0.805

91
Results

• Vending Machine

Reg MUX FU
Control Estimated 240 224 4291
1026 Implemented 152 489 4291
1230
92
Conclusion

• Stages established to date
• - TPN model of OCCAM
• - timing analysis
• - timed reduction set of rules
• - precedence relation/mutual exclusion degree
• - communication cost
• - load balance
• - area estimation
• - methods for estimation of number of FU
• - hardware clock period estimation

93
Conclusion

• Futher works
• - transformation rules for reducing the
  hardware area
• - take into account designers constraints
• - data-flow analisys
• - consider other software components
• - external non-deterministic loops (dynamic
  analysis)
• - architecture generator