Computing Architectures for Virtual Reality

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Computing Architectures for Virtual Reality

• Multiprocessor Servers / Graphic Supercomputers
  vs. PC Clusters Architecture

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Introduction

• VR requires
• fast graphics and haptics refresh rates? graphic
  pipelines
• low latencies? interactivity

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Graphics Rendering Pipeline

• Three functional stages
• Application stage (SW)
• Geometry stage (HW)
• Rasterizer stage (HW)

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Computing Architectures (1)

• Single Host Multiprocessor Server
• Massively parallel architecture
• Multiprocessor?interprocessor communication?shar
  ed memory pool
• Multipipe graphics?parallel rendering?bus based
  fast communication

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Computing Architectures (2)

• Distributed Cluster
• off-the-shelf hardware
• interconnecting network
• scalable

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Distributed VR system architecture problems

• No shared memory pool? low latency network
• Independent graphic accelerator cards? video
  signal synchronization
• If tiled image rendering? composition

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Single Host Multiprocessor Multipipe Servers

• SGI InfiniteReality
• massively parallel architecture
• bus-based broadcast communication to distribute
  primitives
• Graphics subsystem
• Geometry engine,
• Raster Manager,
• Display generator

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SGI InfiniteReality (1)
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SGI InfiniteReality (2)
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SGI Performer (1)

• High performance 3D rendering toolkit
• Use of multiple CPUs,
• Use of multiple graphics pipelines

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SGI Performer (2) - Multiprocessing

• Each stage of the graphics pipeline process can
  then run as a separate process on a separate CPU
• APP
• CULL
• DRAW

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SGI Performer (3) - Multichannels

• Each rendering pipelinecan render
  multiplechannels multiple video outputs

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SGI Performer (4) - Multipipes

• Multiple displays
• synchronized with genlock

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SGI Performer (5) - Hyperpipe

• Temporal Decomposition
• To use with DPLEX ring or chain

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SGI Performer (5) - Frame Synchronization

• pfSync synchronizes the graphics pipeline to the
  frame rate
• DRAW time overruns is specified by the phase
  control? scene management LOD, culling,

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PC Cluster Architecture (1)

• Each node must have access to the same entire
  data set
• real time visualization and interactivity ?
  network latency
• the seamless, synchronized graphic display (image
  reassembly)

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PC Cluster Architecture (2)

• 3 levels of synchronization
• video signal synchronization? genlock
• dynamic data synchronization? network
• frame completion synchronization? swapbuffers
  barrier

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PC Cluster Architecture (3)

• Display szenarios

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PC Cluster Architecture (4)

• 3DLabs

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PC Cluster Architecture - Networks (1)

• Hardware Solutions
• Giga Ethernet (1 Gigabit/s, half duplex)
• Myrinet (2 2 Gigabit/s full duplex)
• ServerNet II (Compaq), ...
• Software Interfaces
• TCP / IP
• PVM, MPI, ...

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PC Cluster Architecture - Networks (2)

• Myrinet
• massively parallel processors (MPP) communication
  technology? specialized communication channels,
  cut-through switches, host interfaces? "OS
  bypass" for low-latency communication

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PC Cluster Architecture - Synchronization (1)

• The following is required to provide a seamless
  image
• each channel must render the same data
• pixel rates must be identical
• the displays must start new images at the same
  time
• swapping of their buffers during the same
  blanking period

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PC Cluster Architecture - Synchronization (2)

• Video Signal Synchronization
• Genlockpixel level synchronization is ensured
  by all graphic pipelines via an (external) sync
  signal? most precise way
• Framelocksynchronizes once per frame at the end
  of the blanking period

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PC Cluster Architecture - Synchronization (3)

• Dynamic Data Synchronization
• 2 types of changing data
• control information direction of view
• changing / dynamic data set information model
  movement
• 3 approaches for distribution
• distribute stimuli
• calculate resulting data centrally and distribute
  
• calculate end graphics data centrally and
  distribute

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PC Cluster Architecture - Synchronization (4)

• Frame Completion Synchronization nodes have to
  wait until are ready to swap buffers? swap
  barrier synchronization
• Multiview

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PC Cluster Architecture - Synchronization (5)

• Net Juggler and SoftGenLock
• based on an input event level parallelization?
  No highbandwidth network necessary
• Synchronization
• Real time Linux
• Fast sync network PAPERS (Parallel Port - 4µs )

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PC Cluster Architecture - Composition (1)

• Display Reassembly in Hardware
• Lightning-2
• connects to graphic accelerators via DVI
• any pixel data generated from any node to be
  dynamically mapped to any location on any display
  
• Sepia 2
• reads back the framebuffer and distributes it
  over a fast network (ServerNet II)

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PC Cluster Architecture - Composition (2)

• Lightning-2
• Pixel Mapping? strip header
• Frame transfer protocol? RS232 back connect for
  sync
• Image composition
• Tiled images
• Colour keying
• Depth compositing

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PC Cluster Architecture - Composition (3)

• Lightning-2 Architecture

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Single Multipipe Graphics Accelerator (1)

• Wildcat III 6210 / Wildcat II 5110

Graphics pipelines
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Single Multipipe Graphics Accelerator (2)
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Single Multipipe Graphics Accelerator (3)

• ParaScale Architecture

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Commercial Cluster Solutions

• SGI Graphics Cluster
• ImageSync
• DataSync

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Commercial Cluster Solutions

• Evans Sutherland SimFUSION

Princeton display wall eight 4-way Pentium-Pro
SMPs with ES graphics accelerators. They drive
8 Proxima 9200 LCD projectors. (1998)
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Commercial Cluster Solutions

• AEC ArsBox
• nodes via Parallelport synchronized
• Redhat 7.1
• SGI Performer
• 100Mbit Ethernet

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Conclusion

• Graphic Supercomputers
• Massively parallel structure
• Expensive
• Established
• PC clusters
• Off-the-shelf hardware
• Distributed ? synchronization