Mul, M' Bakir, J' Jayachandran, R' Villalaz, H' Reed,

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Optical Waveguides Integrated Within a
Sea-of-Leads (SoL) Wafer-Level Package

• Mulé, M. Bakir, J. Jayachandran, R. Villalaz, H.
  Reed,
• K. Martin, P. Kohl, E. Glytsis, T. Gaylord, and
  J. Meindl
• Georgia Institute of Technology

N. Agrawal, S. Ponoth, J. Plawsky, and P.
Persans Rensselaer Polytechnic Institute
Tuesday, June 4th, 2002 IEEE International
Interconnect Technology Conference San Francisco,
CA
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Outline

• Overview of Optical Interconnect Methodologies
• Polylithic Integration Using SoL-OI
• Advantages of Polylithic Integration
• Waveguide Fabrication, Test Results
• Volume Coupler Fabrication, Test Results
• Future Work
• Conclusions
• Acknowledgements

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3
Monolithic Integration Hetero-epitaxial
deposition of III-V sources and detectors on CMOS
chip
Oxide
Contact metal
P Al0.15Ga0.85As Electrode
Detector
LED
Al0.15Ga0.85As Waveguide
Al0.9Ga0.1As Cladding
GaAs
n Ge
GeSi
Si
M. E. Groenert, V. K. Yang, C. W. Leitz, M.
T. Currie, A. J. Pitera, H. Lee, R. J. Ram and E.
A. Fitzgerald, Massachusetts Institute of
Technology
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4
Hybrid Integration Hybrid bonding of III-V
source and detector chips on CMOS chip
Silicon CMOS chip with gold bonding pads
GaAs optoelectronic chip with indium flip-chip
bumps
D. Agarwal, R. Aldaz, G. Keeler, B. Nelson,
J. Harris, and D. Miller, Stanford University
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5
Polylithic Integration (Optical Input/Output
Interconnection) Attachment of Separate SoL CMOS
and III-V chips to High-Density Module
Fiber-to-the-Chip
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6
Polylithic Integration (Optical Clock
Distribution) Attachment of Separate SoL CMOS and
III-V chips to High-Density Module
Module-Level Waveguides,
Couplers
SoL-III-V
SoL-Enabled CMOS
SoL-Level Waveguides, Couplers
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Sea-of-Leads Wafer-Level Package

• Ultra-high I/O density (12k leads per cm2)

A. Naeemi, C. S. Patel, M. Bakir, P.
Zarkesh-Ha, K. Martin, and J. Meindl, Proc.
ISSCC 2001. San Francisco, CA IEEE, pp. 280-281,
Feb. 2001.
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Sea-of-Leads Wafer-Level Package with
OI Polylithic Integration
SoL-Enabled III-V, SoL-Enabled CMOS
c
d
e
a
air
air
b
f
PWB
Printed Wiring Board
a detector b volume grating couplers c
metallization d passivation e waveguide core f
waveguide cladding
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Advantages Polylithic Integration (Optical
Input/Output Interconnection)

• Provides for Fiber-to-the-Chip communication.
• Eliminates impact of optical interconnect
  technology on conventional CMOS manufacture.
• Integration of SoL technology allows very high
  chip-to-chip communication bandwidth due to
  high I/O density.
• Integration of heat-sinks allowed for heat
  removal in both III-V and CMOS chips.
• Separation of active components simplifies
  design, manufacture, and packaging of
  fiber-to-module connector .

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Advantages Polylithic Integration (Optical Clock
Distribution)

• Eliminates need for chip-level source (only
  waveguides, gratings, and detectors).
• Eliminates need for global clock drivers, local
  multipliers in intra-chip clock distribution.
• Delivers clock signal free from clock
  buffer-induced short-term jitter to silicon
  detectors.
• Eliminates clock skew due to unpredictable
  differences in signal arrival time.

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Waveguide/Grating Configurations
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Volume Manufacturing

• Approach 1 Lamination of Pre-Exposed Sheets
• Expose photopolymer to form grating using
  interferometric techniques
• Laminate photopolymer sheet to desired substrate
• Cure substrate
• Grating definition accomplished independently of
  substrate manufacture
• Issue waveguide/photopolymer adhesion

• Approach 2 Spin-On Photopolymer
• Spin-on photopolymer
• Expose photopolymer to form grating using
  interferometric techniques
• Cure substrate
• Grating definition accomplished in conjunction
  with substrate manufacture

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Coupling Efficiency vs. Length (Rigorous Coupled
Wave Analysis)
Lgrating _at_Max CE
30 um 130 um 450 um 875 um
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Coupling Efficiency, (CE)
?nfringe 0.1, Grating-in-Waveguide
?nfringe 0.1, Grating-atop-Waveguide
?nfringe 0.02, Grating-in-Waveguide
?nfringe 0.02, Grating-atop-Waveguide
0 100 200 300 400 500 600 700 800
900 1000
Grating Length, Lgrating (um)
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Advantages of SoL OI

• Use of board-level focusing grating couplers for
  board-to-chip coupling allows for reduction
  in beam size and alignment concerns.

• Receiving couplers located within package can be
  sized such that SoL-to-board misalignment is
  addressed without concern for via blockage.

• Grating couplers performing waveguide-to-detector
  coupling can be placed immediately above
  detectors.

• Enhanced testability is provided by wafer-level
  test of optical interconnection.

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Advantages of SoL OI

• Sacrificial polycarbonate material decomposes
  
• to leave embedded air-gap.
• Integration of air-gap allows for increased ?n
  in polymer waveguide interconnect
• ?n 0.03 ? 0.54

• Can apply embedded air-gap technology to both
  PWB and SoL technologies due to low-temperature
  decomposition (160 C).

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Higher ?n Smaller Bend Radii
b)
a)
Waveguide arc of 20 µm bend radius in two
technologies

• Polymer waveguide core, air cladding (?n 0.54)
• Polymer waveguide core, polymer cladding (?n
  0.03)

(? 1.55 µm, wwg 1 µm, Ey component )
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Waveguides with Embedded Air-Gap Fabrication
Process
I/O Pad
I/O Pad
SiO2
1
5
Waveguide Core
Overcoat
2
6
3
Embedded Air-gap
Photosensitive Polycarbonate Composite
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4
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Waveguides with Volume Couplers Fabrication
Process
Photosensitive Polycarbonate Composite
I/O Pad
I/O Pad
SiO2
5
1
Waveguide Core
2
6
Overcoat
Laminate Photopolymer
7
3
Embedded Air-gap
Grating
Waveguide
8
4
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SoL OI Cross-Section (Waveguide, Air-Gap)
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SoL OI Cross Section Optical Power Coupling

• Butt-Coupled from Fiber-Coupled Laser Diode

Air
Waveguide
SiO2
Silicon Substrate
(Overcoat Removed)
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SoL OI Top View
Compliant Leads
Waveguides
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SoL OI Top View (Detail)
Compliant Lead
Buried Air-gap Region
Waveguide
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SoL Waveguide-on-SiO2 Loss Measurements

• Measured losses compare with previously-reported
  values

S. Ponoth, N. Agarwal, P. Persans, and J.
Plawsky, Mat. Res. Soc. Symp. Proc., vol. 637,
pp. E4.8.1-E4.8.6, 2001.
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Interferometric Recording Configuration
UV Laser
Spatial Filter
Collimating Lens
Mirror
Shutter
Coupler
Mirror
Prism
Adjustable Beam Splitter
S. M. Schultz, E. N. Glytsis, and T. K.
Gaylord, Opt. Lett., vol. 24, pp. 1708-1710,
Dec. 1999.
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Surface-Normal Volume Coupler (Grating-atop-wavegu
ide)
1.00 0.96 0.92 0.88 0.83 0.79
Transmitted Intensity (Normalized)
0
-6.0
-4.0
-2.0
-0.0
4.0
2.0
Incident Angle, ? (deg)
Dupont photopolymer grating atop Polyset epoxy
waveguide

• Issue Adhesion of Dupont photopolymer to
  Polyset epoxy

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Design, fabricate phase mask for parallel
fabrication of optical couplers
Future Work Grating Array Definition

• Overcomes throughput limitations of
  interferometric
• recording configuration.
• Permits board-, wafer-level fabrication of
  coupler arrays.

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Conclusions
Polylithic Integration New concept for
integration of optical interconnection into
microelectronics.

• Wafer-level batch process.
• Compact packaging of electrical/optical system.
• Allows for integration of conventional heat
  removal, power supply techniques.
• Minimizes impact of optical interconnect
  technology on CMOS manufacture.
• Buried air-gap maximizes refractive index
  contrast for tighter bends, increased density.
• Volume coupler integration mitigates alignment
  concerns for board-to-chip coupling.
• Flexible fabrication process, adaptable to
  different polymer, grating technologies.

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Acknowledgements

• This work is funded by SRC and MARCO

Thank You !
Contact Information Tony Mule tvmule_at_ieee.org
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Backup
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Contributions
Georgia Institute of Technology A. Mulé
Concept, OI Technology Development M.
Bakir SoL Technology Development R.
Villalaz Volume Coupler Design, Fabrication J.
Jayachandran Air-gap Material Development H.
Reed Air-gap Material Development K.
Martin Advisor P. Kohl Advisor E.
Glytsis Advisor T. Gaylord Advisor J.
Meindl Advisor
Rensselaer Polytechnic Institute N.
Agrawal Waveguide Material Development S.
Ponoth Waveguide Material Development J.
Plawsky Waveguide Material Development P.
Persans Waveguide Material Development
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Projections for Short-Term Jitter
A. V. Mule et al., submitted, TVLSI, Apr.
2001.
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Buried Air-Gap Cross-Section
Overcoat
40 um
Air-Gap (No Waveguide)
4 um
Substrate
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Volume Manufacturing (Laminate Sheets)
Source Optical Crosslinks
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Intellectual Property
Guided-Wave Interconnection with Air-Gap
Technology T. Mulé, P. A. Kohl, E. N. Glytsis,
T. K. Gaylord, and J. D. Meindl, Optical
Waveguides with Embedded Air-gap Cladding Layer
and Methods of Fabrication Thereof, U. S.
Utility Application, filed Feb.
2002. Wafer-Level Batch Package Optical
Interconnect Technology T. Mulé, M. Bakir, H.
Reed, S. M. Schultz, C. Patel, K. P. Martin, P.
A. Kohl, E. N. Glytsis, T. K. Gaylord, and J. D.
Meindl, Guided-Wave Optical Interconnection
Using Volume Grating Coupler and Air Gap
Technologies Embedded Within a Microelectronic
Package, U.S. Utility Application, filed Feb.
2002.
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Intellectual Property (contd)
MCM/PWB/Backplane Optical Interconnect
TechnologyT. Mulé, M. Bakir, H. Reed, S. M.
Schultz, R. Villalaz, P. A. Kohl, E. N. Glytsis,
T. K. Gaylord, J. D. Meindl, Passive Thin-film
Integrated Optical Guided Wave Interconnection
Layer Using Air-Gap and Volume Grating Coupler
Technologies for Multi-chip Modules, Printed
Wiring Board, and Backplane Applications and
Method, U.S. Provisional Patent Application,
Docket 2476PR, Jan. 2001. Low-k Nano Air-Gap
Optical Interconnect TechnologyT. Mulé, A.
Padovani, S. A. Bidstrop, P. A. Kohl, E. N.
Glytsis, T. K. Gaylord, and J. D. Meindl,
Monolithic Chip-level Optical Waveguides Formed
from Low-k Nano Air-gap Inter-layer Dielectric
(ILD) Materials and Methods, U.S. Provisional
Patent Application, Docket 2487PR, May 2001.
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Intellectual Property (contd)
Optoelectronic Probe Card Technology T. Mulé, H.
Thacker, M. Bakir, K. P. Martin, T. K. Gaylord,
P. A. Kohl, and J. D. Meindl, High I/O Density
Optoelectronic Probe Card for Wafer-level Test of
Electrical and Optical Interconnect Components
and Methods of Fabrication, U. S. Provisional
Patent Application, Docket 2635, Mar. 2002.
Phase Mask TechnologyT. K. Gaylord, E. N.
Glytsis, and J. D. Meindl, Phase mask consisting
of an array of multiple diffractive elements for
simultaneous accurate fabrication of large arrays
of optical couplers and method of making same,
U.S. Patent Office Patent Application No.
09/848,935 filed May 3, 2001.
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Intellectual Property (contd)
Diffractive Grating Coupler and MethodS. M.
Schultz, T. K. Gaylord, E. N. Glytsis, and N.
Hartman, Diffractive Grating Coupler and
Method, U. S. Patent No. 6285813 assigned to
Georgia Tech Research Corp., Sept. 2001.