Austin Lesea

1
Platform FPGAs for Wireless

• Austin Lesea
• Principal Engineer
• IC Design

2
Killer Apps

• 2.5, 3 and 4G Wireless
• Video Processing
• SDR
• Network Processors(?)
• Storage Systems
• Telecom Transmission Systems

3
Design Productivity Gap
Gates/cm2 Moores Law (59 CAGR)
3,830K
2,410K
1,520K
Log Scale
957K
603K
305K
380K
244K
195K
156K
Average Cell-based Design Start (25 CAGR)
125K
100K
0.6µ 1994
0.5µ 1995
0.35µ 1996
0.25µ 1997
0.2µ 1998
0.15µ 1999
Growing gap between whats designable and whats
manufacturable
Source VLSI Technology
4
Alternative Interpretations of the Design
Productivity Gap

• Design methodology is falling behind.
• We must make design more efficient
• Higher-level capture better automation
• The design problem is too big for one person.
• We must make design teams effective
• Transistors are cheap.
• Spend them for something more valuable (like
  design time)

5
Complex ASIC DesignThe Shrinking Window of
Innovation
Synthesis
16

• Average iterations between design and layout 20

(Source Electronic Systems Jan 99)
6
Challenges of UDSM IC Design

• Device modeling
• Interconnect Modeling
• Holistic simulation
• Mixed Signals
• Integration of IP
• Mask making
• Mask costs
• Cost of failure

7
Typical 20-Layer PCBA Very Tough Design Problem
Courtesy, NetCore Systems.
8
What are Platform FPGAs?

• A solution that provides the
• Ability to integrate a wide variety of hard
  soft IP
• Ability to serve multiple applications
• Ability to support upgrades in design and in the
  field

Driven by IP, enabled by silicon, empowered by
software
9
Xilinx IP Solutions
Benefits Time-to-Market, Productivity
Benefits Engineering Productivity
Benefits Quality, Productivity, Time-to-market
Benefits Reduced Cost, Faster Time-to-Market
IP Cores and Reference Designs
Design Reuse
IP Delivery Tools
Integration Expertise

• More Cost-effective than ASICs!
• 75 of Netlists cost less than 10K

10
Xilinx IP Center, wireless cores
Reed-Solomon Encoder Decoder IS-95 A/B
Convolution Encoder IS-95 A/B Viterbi
Decoder Complex Fast Fourier Transforms/ Inverse
Fast Fourier Transforms
FFT16 FFT64
FFT256 FFT1024
Distributed Arithmetic FIR Filter Hilbert
transform Comb Filter FIFOs with Block
RAM Distributed RAM RAM Adaptive Differential
Pulse Code Modulator Broadband Satellite
Modulator Numerically Controlled Oscillator ..
More to come
11
Efficient Design Verification

• HDL Simulation
• Functional Simulation (RTL)
• Timing Simulation
• Static Timing Analysis
• Debug
• Probe
• Chipscope ILA - In-System Verification
• Board Level Simulation / Verification

12
Board Level Verification

• Static Timing Analysis
• Supported through STAMP models
• STAMP models the I/O behavior of the Xilinx
  device
• Simulation
• Support through LMG Smart Models
• Works for any verification tool that is
  LMG-compliant
• Signal Integrity
• IBIS Models for all devices available from
  xilinx.com

13
Incremental Design Methodology

• Conventional Flow (if Block E changes)
• Incremental Design Benefits (if Block E changes)
  

3. Then Place Route Everything Again
2. Synthesize Everything Again
1. Edit the HDL for Block E
2. Only Synthesize Block E using Block-Level Synt
hesis
3. Then Place Route only Block
E using High-Level Floorplanner
1. Edit the HDL for Block E
14
Compile One Million Gates in Under One Hour
30,000
v3.1i
Constant Software
Runtime Improvement
Current release is now 16X faster than v1.4
25,000
20,000
Gates per Minute
15,000
v2.1i
10,000
v1.5i
5,000
v1.5

• Version 1.0 using a 4025E device compiled at 17
  gates per minute.
• Version 3.1i with a XCV1000E compiles at 27,000
  gates per minute!

15
FPGA Performance

• Only getting better
• ASICs are harder an harder to test
• 0 test logic in an FPGA
• hard IP for best performance
• serdes
• uP
• BRAM
• DCM

16
ActiveInterconnect Technology
17
Platform FPGA RoadmapProcess Technology
0.07µ
0.10µ
Virtex-II Series
Mauna Loa
0.13µ
1.5V core
0.15µ
1.5V core
0.18µ
1.8V core
0.22µ
2.5V core
2004
2001
2002
2003
2000
1998
1999
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Platform FPGA RoadmapPowerPCTM Embedded
Processor Core
Capabilities / Performance
2002
2003
2001
2004
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PowerPC 405 Specifications
Core Size
20
Platform FPGA RoadmapHigh-Speed Serial I/O
Whitney
5.0Gb Serial Channel Bonding 20 Gb/s IO
Capabilities / Performance
Mauna Loa
3.125Gb Serial Channel Bonding 10 Gb/s IO Stds.
2002
2003
2001
2004
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Mauna Loa OverviewNew PowerPC and 10Gb Serial
Cores
IP-Immersion Fabric
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Advanced 0.13um CMOS

• World Logic Partnership
• IBM, Xilinx, UMC, Infineon
• Ultra-high Speed 92nm Transistor Technology
• 8 Layer Cu combined with Low K Dielectric
• 12 Volume Production on Three Continents

23
Wireless Product Examples

• Development Systems
• Customer product

24
Applied Signal Technology

• "we make a variety of equipment including IF, RF,
  processing equipment, voice grade channel
  processors, mobile radio signal processing
  systems and wide band digital signal processors.
  Our designs are used in a wide variety of telecom
  applications, including cellular, modems and fax,
  digital microwave radio, satellite communications
  and digital TV. All of this equipment is
  characterized by a high degree of integration,
  fast algorithmic processing, and an extreme
  amount of flexibility. We are currently
  completing a project were each of our advanced
  demodulator ASIC designs was enhanced, converted
  to generic VHDL and ported to a Virtex XCV1000.
  Virtex has the density, speed and system level
  features like block RAM and DLLs that make it
  competitive with ASIC technology. Sean Caffee

25
Vendors of DSP Platforms Using Virtex Series FPGAs

• http//www.nallatech.com/products/dime_professiona
  l/ballyriff/index.htm
• http//www.gvassociates.com/page7.html
• http//www.pentek.com/products (Search for FPGA
  products)
  
• http//www.trellisware.com/ (Look for ASPECT
  board)
• http//www.spectrumsignal.com/
• http//www.entegra.co.uk/
• http//www.hunteng.co.uk/info/fpga-dsp.htm
• http//www.transtech-dsp.com/sharc/asp-m93.htm

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GV Associates
27
Pentek, Inc
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TrellisWare
TrellisWare Technologies ASPECT board offers the
largest reconfigurable logic array on the
market today. With over 16 million system gates,
the ASPECT is capable of more than 400
billion operations per second (16-bit fixed-point
MACs). At the heart of the ASPECT Board is an
array four Xilinx Virtex-E Series FPGAs. The
Virtex-E Series FPGAs offer the largest densities
of any reconfigurable logic device available. The
ASPECT Board employs an advanced
reprogrammable interconnect scheme. Each FPGA in
the array contains from 1.5M to over 4M
equivalent gates. This approach also provides
full connectivity to on-board peripherals, RAM
and I/O.
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Nallatech
HighLights Four 12bit Analog Input Channels Up
to 105 MSPS Conversion rate Single-ended or
Differential Inputs AC/DC Coupled Input Options
VirtexE - support for XCV400E to XCV3200E
128MBytes SDRAM 4 Digital I/O Lines for Control
and Triggering Flexible Clock Arrangements
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31
Q A

• Questions?
• Austin Lesea, Principal Engineer, IC Design,
  austin.lesea_at_xilinx.com