MOSFET modeling for RF circuit design

1
MOSFET modeling for RF circuit design

• Nobuyuki Itoh
• Semiconductor Company
• Toshiba Corporation

2
Recent Progress of MOSFETs Performance
CMOS VLSI Symp. 2004 fTmax209GHz
(Intel) fTmax243GHz (IBM) SiGe Bipolar BCTM
2004 fTmax231GHz (Hitachi) fTmax230GHz (ST
micro)
3
Contents
STI Stress For Small Geometry Device
VTH based model or Surface potential model
Gate Insulator
SiO2?SiON Flicker Noise Increasing
Gate
STI
STI
S/D Diffusion
P-well
Thermal Noise Increasing due to Hot Carrier
N-well
P-sub
4
VTH based model or Surface potential model
VTH based model or Surface potential model
Gate Insulator
Gate
STI
STI
S/D Diffusion
P-well
N-well
P-sub
5
Two types of compact model
Many Differences
By Ref.1
6
Difference btw simulation and measurement(1)
BSIM4
EKV
Large (W/L10/10)
n-factor vs. Vgs
BSIM4
EKV
Short (W/L10/0.14)
7
Difference btw simulation and measurement(2)
gm vs. ID
8
Basic analog characteristics
By Ref.2
9
VTH based model or Surface potential model
Surface potential model seems better than VTH
based model for analogue design.
but
Surface potential model is not so popular right
now
10
Flicker noise
Gate Insulator
SiO2?SiON Flicker Noise Increasing
Gate
STI
STI
S/D Diffusion
P-well
N-well
P-sub
11
Flicker Noise due to scaling
Scaling ? Thinner gate oxide ? Gate leakage
increasing ? SiO2 to SiON
12
Cause of flicker noise degradation
N profile using NO annealing
By Ref.6
13
N profile control
14
Flicker noise
Flicker noise is always problem in recent scaled
MOSFET
but
It seems not problem for its modeling
15
STI stress
STI Stress For Small Geometry Device
Gate Insulator
Gate
STI
STI
S/D Diffusion
P-well
N-well
P-sub
16
STI Stress
By Ref.8
17
gm degradation due to STI stress
18
Inverter performance due to STI stress
Mobility large Capacitance small
Mobility small Capacitance large
Mobility small Capacitance small
Mobility large Capacitance large
Which is better performance?
19
STI stress
STI stress was modeled by BSIM4.
but
It is not confirmed practical layout yet.
20
Scalable substrate network
Gate Insulator
Gate
STI
STI
S/D Diffusion
P-well
N-well
P-sub
21
Normal BCIM3 model
s11
s21
22
MOSFETs Equivalent Circuit for RF
To realize scalable model, device geometry has to
keep scalability
Have to define target layout of MOEFET ?R is
defined by distance btw channel to contact
By Ref.3
23
Target Layout
For Toshiba 0.13 mm CMOS
24
Scalable Model (Lg dependence)
25
Scalable Model (Wg dependence)
26
Scalable Model (Vds dependence)
27
Scalable Model (Vgs dependence)
28
Scalable substrate network
Scalable substrate network was realized by
in-house design tool.
but
More accuracy and layout freedom is necessary
29
Thermal noise
Gate Insulator
Gate
STI
STI
S/D Diffusion
P-well
Thermal Noise Increasing due to Hot Carrier
N-well
P-sub
30
Expressions
31
g vs. Lg
In the case of sub-0.1-micron MOSFET, g is larger
than 4. 90nm ?4.7 65nm ?6.1 in the estimation
32
Noise measurement for Sub-0.1-micron NMOS
de-embeded capacitance by measurement
gate resistance by calculation
33
Measurement data
34
Empirical formula
Empirical equation
35
Difference between this work and others
36
How affect to circuit performance estimation
LNA ? well known directly affect to
circuit performance estimation
VCO ? Also affect to circuit performance
estimation
37
VCO noise expression
38
Bipolar VCO
1MHz offset
Quit good correlation between measurement data
and calculated data..
39
Comparison of VCO noises
Adapt g value which calculated by the empirical
equation to several kinds of integrated
MOSFET-VCO goptimized difference between
measured and calculated is within /- 2dB
(average) g0.67(fixed) difference between
measured and calculated is large! Need suitable
g value for thermal noise of MOSFET
1MHz offset
40
Summary

• Surface potential model seems better than VTH
  based model for analog circuit design due to its
  continuous characteristics. It needs entire
  discussion which model has to be chosen.
• Scalable substrate network model has already been
  realized for limited layout. But it might be
  need more layout freedom.
• Flicker noise increasing of SiON gate insulator
  is problems for performance. But accuracy of
  model is not issue.
• STI stress model has been not popular, yet. We
  need more experience.
• Thermal noise model is still issue. g is
  increasing due to scaling. It is the one of most
  important issues for RF analog designe.

41
Acknowledgments
Great Tanks to Dr. Sadayuki Yoshitomi Ms.
Hisayo S. Momose Mr. Kenji Kojima Mr. Tatsuya
Ohguro of Semiconductor Company, Toshiba
Corporation
42
References
1. R.van Langevelde, et, al., "RF Performance
and Modeling of CMOS Devices," Educational
Sessions Workbook of CICC, September, 2003 2.
M.Bucher, "Analytical MOS Transistor Modeling for
Analog Circuit Simulation," The Doctor Thesis of
EPFL, pp.140, Lausanne, 2000 3. N.Itoh, et.
al., "Scalable Parasitic Components Model of CMOS
for RF Circuit Design," IEICE Transaction of
Fundamentals, vol. E86-A, No.2, pp.288-298,
February, 2003. 4. H.Kimijima,et. al.,
"Improvement of 1/f noise by using VHP(Vertical
High Pressure) oxynitride gate insulator for
deep-sub micron RF and analog CMOS," Symp. VLSI
Tech. Dig., pp.119-120, Kyoto, 1999. 5. M.
Rodder et., al, SSDM 1998 6. T.Ohguro, et. al.,
The impact of oxynitride process, deuterium
annealing and STI stress to 1/f noise of 0.11 mm
CMOS, Symp. VLSI Tech. Dig., 2003. 7.
T.Ohguro, et. al., A study of analog
characteristics of CMOS with heavily nitrided NO
oxynitrides, Symp. VLSI Tech. Dig., 2001. 8.
R.A.Bianchi, et. al., Accurate Modeling of
Trench Isolation Induced Mechanical Stress
effects on MOSFET Electrical performance,
Proceedings of IEDM, 2002. 9. Y.P. Tsividis,
Operation and Modeling of the MOS Transistor,
NewYorkMcGraw-Hill, 1988. 10. A.J.Scholten,
et. al., Accurate Thermal Noise Modeling for
Deep-Submicron CMOS, Proceedings of IEDM,
1999. 11. G. Knoblinger, et. al., A New Model
for Thermal Channel Noise of Deep-Submicron
MOSFETS and its Application in RF-CMOS Design,
IEEE Journal of Solid-State Circuits, vol.36,
No.5, pp.831-837, May, 2001. 12. A.J.Scholten,
et. al., Compact modeling of drain and gate
current for RF CMOS, Proceedings of IEDM,
pp129-132, 2002. 13. G. Knoblinger, et. al.,
Thermal Channel Noise of Quarter and Sub-Quarter
Micron NMOS FETs, Proceedings of ICMTS,
pp95-98, 2000. 14. A.A. Abidi, High-frequency
noise measurements on FETs with small
dimensions, IEEE Trans. Electron Devices,
vol.ED-33, pp1801-1805, Nov., 1986.