SDO CDH Subsystem Mission PDR

1
SDO CDH SubsystemMission PDR

• Jack McCabe, Code 561
• SDO CDH PDL
• SDO CDH PDT
• Schumacher, Pack, Culver, Dailey, Haghani, Folk,
  Li, Hovmand, Ballou, Hawkins, Winkert, Hestnes,
  Calderwood, Nearhoof, Luers, Smith, Younger
  Padgett

2
MRD v5.0 Level 2 Driving Requirements

• 2.2.2 Fault Tolerance
• Design shall be either
• Single fault tolerant and meet minimum success
  criteria. Or
• Employ sufficient testing/analysis to ensure
  system reliability where fault tolerance
  graceful degradation does not exist.
• Interpretation of this requirement (graceful
  degradation ) leads to cross strapping,
  redundancy, robust system design.
• 2.3.2 Radiation
• TID 400 Krad 100Mils, 40 Krad 200Mils
• SEE Destructive LET gt 100 Mev
• SEE Non Destructive LET lt37 Mev
• 4.4.2.2 Ka Band
• 150 Mbps continuous I Q science data to the
  ground.
• ATMEL device TSS901E
• Autonomous HSB link re-sync.
• 4.4.3.1 Data System
• Distributed Architecture
• Common nodal power supply, power switching, and
  backplane protocol.
• 4.4.3.6.3.2 Stored telemetry
• 90 Mbytes minimum of Recorder Space.
• 4.4.3.7.2 Bit error

3
CDH Subsystem Top Level Design

• Primary Subsystem Responsibilities
• Serve as the S-Band uplink downlink interface
  between the ground and the observatory.
• Serve as the Ka-Band downlink interface between
  the instruments and the ground.
• High Speed Bus (HSB) End To End oversight.
• Serve as spacecraft 1553 Bus controller.
• Provide the main computing power for the
  spacecraft.
• Provide spacecraft Bulk Memory.
• Provide for limited 28V power distribution.
• Provide for limited spacecraft telemetry
  gathering and processing.
• Subsystem Components
• S_Comm Card S-Band uplink downlink interface,
  28V power distribution control, telemetry
  gathering and processing.
• Ka_Comm Card Ka-Band downlink interface.
• SBC BMC Cards Main computing power, 1553 Bus
  controller, Bulk Memory.
• DCDC Cards Local Subsystem power.
• Backplane Local Subsystem data transfer.
• PCC LPSC Provided by 563 for primary power and
  service switching
• Subsystem Redundancy
• The CDH Subsystem is fully redundant and its
  components are housed in two identical boxes.
• Each box is comprised of three independent
  functional entities, coupled by a local Subsystem
  Backplane

4
Implementation Architecture

• Three independent functional units enclosed in
  the same box
• Single Board Computer, DC/DC and BMC card
  function as the main Spacecraft Processor and bus
  controller.
• SDN-based S Comm Uplink/Downlink card, provides
  command and housekeeping telemetry interface to
  S-band Transponders.
• Ka Comm card, receives science data from
  instruments via ATMEL 1355 interface, Formats,
  encodes and transmits IQ serial data to Ka
  Transmitter for downlink.
• S Comm card controls a separately powered LPSC
  which is used to provide power to remaining CDH
  components
• Allows for power switching to SBCs without
  reliance on 1553 bus or hardware decoded commands
• Hardware commands exist to reset S Comm card,
  reset PSE, and power cycle PSE services
• S Comm card receives un-switched power, but LPSC
  switch card power is switched by PSE, providing
  fault isolation in the event of S Comm card
  failure
• Both Ka Comm and S Comm cards provide
  cross-strapped interfaces to their respective RF
  systems
• S Comm receives real time telemetry over 1553
  bus, and playback over Serial Port. Serial port
  is cross strapped from Bulk Memory Card
• Ka Comm provides for two 100Mbit links to each of
  the three instruments. Instruments have option to
  spread data over both links or just one link
  (baseline is two links).

5
Changes since SCR

• Added Bulk Memory Card to subsystem architecture
• MRD (4.4.3.6.3.2) requirement for 90 Mbytes of
  storage.
• SPN split into two card (PCC LPSC)
• MRD (4.3.3) Power Distribution
• Power sequence circuit to accommodate ACTEL FPGA
  inrush GIDEP alert.
• ACTEL guide up alert for possible In-rush
  problems.
• Added 2.5V voltage to CDH backplane design to
  accommodate ACTEL FPGA inrush guide up alert
• ACTEL guide up alert for possible In-rush
  problems.
• Ka Card DL ASIC to generate serialized I Q
  instead of previous baseline to use commercial
  serializer
• Radiation issues made previous part unreliable
  for baselined BER clock distribution.
• Clock circuit redesign to Ka card.
• Radiation issues made previous part unreliable
  for baselined clock distribution. And MRD
  (4.4.2.2) for 150 Mbps downlink
• Added HSB Link resync capability
• Backplane bus protocol changed from Simple Bus
  to cPCI.
• MRD (4.4.3.1) program decision to use a
  standard bus protocol over non-standard bus
  protocol.

6
SDO Electrical Architecture
28V Power to ACS sensors, actuators heaters
Ka XMTR A
HMI

HMI Optics CEB
High Speed Data Ka Band
ACE A
Ka XMTR B
Power Switching
RT
DC/DC Converter
Waveguide Switch
CSS
from Ka Comm B
HMI Inst Electronics
DC-DC Converter
RT
Bulk Memory DC/DC Converter
BC
ACE SDN
S/C Processor
AIA
RT

to High Gain Antennae
GTs
RT
RWA I/O
Uplink/Downlink S Band SDN
to S- Band
EVE
H/W decoded cmds
ESP
AEB
Prop Pyro board
DC-DC Converter
4 Optics CEB
Thermistors, HGA sensors
EVE IEM (incl. SDN)
28V power
MEGS
Engine Valve Driver boards
Pwr Switching
GCE
CDH A
RT
IRU
RT
Pwr Switching
RT
DC-DC Converter
1553 Bus
Propulsion
RT
Gimbal Interface
RT
RT
Engine Valve Driver boards
Prop Pyro board
PSE SDN
Battery Module
3 Output Modules
PSE SDN
Deploy Circuits
Solar Array Module
Solar Array Module
DC-DC Converter
DC-DC Converter
3 Output Modules
RWA I/O
CSS
ACE SDN
28V Power to Gimbal drives, Instrument Module
thermal control
PSE
RT
DC-DC Converter
Power Switching
28V power
28V power
ACE B
Solar Array
Solar Array
28V Power to ACS sensors, actuators heaters
Battery
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CDH Subsystem Architecture Box 1
Local CDH Backplane Region - 1
Local CDH Backplane Region - 2
Local CDH Backplane Region - 3
(2.5V, 3.3V, 5V, /- 15V)
LPSC
PCC
SDN
S COMM
DCDC/ BMC
SBC
DCDC
Ka Comm
(2.5V, 3.3V, 5V)
(2.5V, 3.3V, 5V)
RT
BC
RT
S/C 1553 Bus AB
Instruments 1355 3 x 2 port HSB IF
Playback Serial IF - A
Playback Serial IF - B
Ka Band LVDS HSB IF AB
Playback Serial IF - B
S Band Uplink IF AB
Switched 28 V
Switched 28 V CDH Region 2-B
Switched 28 V
Switched 28 V CDH Region 3-B
S Band Downlink IF AB
Switched 28 V S Band TX AB
Telemetry Collection Discrete Commanding AB
Switched 28 V Heater Control
Dual PSE AB Switched 28 V
Dual PSE AB UnSwitched 28 V
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Heritage

• Level of heritage in the SDO CDH Subsystem
• Region One (S Band Comm, Power, Switching)
• SDN based S_Comm card
• Functional Concept has MAP/EO-1 heritage
• Processor however is new (Cold fire rather than
  UT69R000)
• Backplane
• Backplane Interface is cPCI (standard used on
  SWIFT). Flight applications that comply with
  standard have been imposed on interface.
• Power
• PCC and LPSC have functional heritage with
  MAP/EO-1
• Region Two (Processor/Recorder/cPCI Backplane)
• Functional capabilities have standard flight
  heritage.
• Requirements for SBC can be met with commercially
  available designs
• Bulk Memory has functional heritage with DRAM and
  serial playback capabilities.
• cPCI interface is to be commercial standard.
• Region Three (HSB/Ka_Comm)
• ATMEL 1355 device has limited heritage from
  STEREO
• Data rate (150Mbps) with no storage and
  continuous playback has no heritage
• Subsystem Enclosure and card design
• Will have maximum manufacturing heritage with
  MAP/EO-1.

9
Technical Resources
10
S-Band Telemetry Functional Flow
(From SDO Systems PDR)
11
S_Comm Hardware Commands
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Processing Element Development Strategy

• Single Board Computer (SBC)
• The Single Board Computer (SBC) will be procured
  as a commercial item (i.e.. An item that is
  available for sale in the commercial marketplace)
• SBC requirements are captured in the following
  SDO documents based on numerous meetings with SDO
  subsystem engineers and limited market research
  of known vendors
• Performance Specification - 464-CDH-SPEC-0012
• Statement of Work (SOW) - 464-CDH-LEGL-0008
• Spec and SOW incorporated into a
  Request-for-Offer (RFO) package to industry.

• Bulk Memory Card (BMC)
• Interface to SBC via cPCI bus (32-Bit, 33MHz)
• SBC ICD/Specification
• Provide a minimum 90 Mbytes of data storage
• MRD Level 2 Directed
• Allow playback of stored telemetry directly to
  S-COMM card with a maximum clock rate of 2 MHz
• S-COMM Card ICD/Specification
• Provide throughput for power from DC/DC card to
  SBC
• DC/DC Card ICD/Specification
• Support Reset interface to SBC
• SBC procurement
• Support 1553 BC Interface
• SBC procurement

13
Time

• What is the Scope of Observatory Time
• Relative Accuracy
• 0.010 Sec over period of 1Sec
• Absolute Accuracy
• Observatory to ground to within 0.1 Sec
• Time Adjustment
• lt 100 uSec over period of 1 Sec
• HMI requires smooth time adjustment
• Ground time correlation
• Time distribution
• Time verification
• Who is responsible for Time
• The CDH is Master Clock Keeper
• Reference documents
• 464-SYS-REQ-0004
• 464_CDH-SPEC-0042
• Where is it used in the Subsystem
• The CDH maintains, adjusts and distributes time
  to instruments, S/C subsystems and ground systems.

• How is time maintained
• CDH maintains time using both hardware and
  software.
• FSW uses the hardware counters, the MET, the UTCF
  and the leap seconds to represent one single
  value S/C UT.
• Adjustment capabilities include
• Course adjustment of S/C UT
• Fine adjustment of S/C UT
• Constant adjustment to reduce S/C UT drift with
  respect to UTC.
• Hardware supports the S/C UT to UTC correlation
  method that will meet the mission time accuracy
  requirements.

14
Ka-Band Telemetry Functional Flow
to HGA A
Waveguide switch
to HGA B
Note While the arrows do not show it, there is
flow control back to the instruments from the Ka
Comm Card.
15
HSB Requirements/Specification Overview

• REQUIREMENTS
• Transfer science data from Instr. to Ka Comm
• 3 instruments rates
• AIA 67 Mbps
• EVE 7 Mbps
• HMI 55 Mbps
• Fault tolerance
• Primary/redundant Ka Comm boards, cold-spared
• Paired links from each instrument to each Ka Comm
• Implement a Link resync method
• Data flow management
• Perform data rate quota enforcement via TDM table
• Utilize
• Atmel TSS901E (SMCS332)
• Atmel T7906E (SMCS116)

• SPECIFICATIONS
• Protocol layers (bottom to top)
• Physical
• Spacewire cable/connector compliant
• Signal
• Cold-spare LVDS and/or LVDM transmitters (TBR)
• Cold-spare LVDS receivers
• Data/Strobe
• Character
• IEEE 1355 compliant
• Spacewire compliant without Time codes
• Exchange
• Atmel 1355 compliant
• Packet
• IM_PDUs from instruments to Ka Comm
• No packets from Ka Comm to instruments
• Just null flow control characters
• Network
• Paired point to point IEEE 1355/Spacewire links

16
Data Flow Management

• Basic Ka Comm function is a 61 mux
• Receive IM_PDUs simultaneously on up to 6 input
  ports
• Build CADUs from IM_PDUs
• Multiplex CADUs onto 1 output port to RF
  modulator
• Ka Comm also ensures instrument rates are not
  exceeded via 1300 slot TDM table
• Each slot holds 3-bit value of IM_PDU port to
  output next
• Default slots values copied from PROM to RAM
  after reset
• Each slots value can be changed by ground
  command
• 1300 slots provides for data rate limit selection
  with 0.1 Mbps resolution for 150 Mbps CADU output
  rate
• HSB performs data rate quota enforcement per Ka
  Comm TDM table direction

• 1300 slot TDM table
• A-1 AIA channel 1
• A-2 AIA channel 2
• E-1 EVE channel 1
• E-2 EVE channel 2 (Not used nominally)
• H-1 HMI channel 1
• H-2 HMI channel 2
• fill Fill CADU
• Each slot represents 1 CADU
• 109 usec per slot
• 16,352 bits _at_150 Mbps
• 1 IM_PDU per CADU
• Slot assignments are configurable
• 1300 slots provides 0.1 Mbps per slot
• CADUs _at_ 150 Mbps IM_PDUs _at_ 130 Mbps
• 130 Mbps / 1300 slots 0.1 Mbps per slot

17
Testing

• Ka Downlink Card
• NTGSE, FEPS, Instrument Data Simulator (Limited
  functionality for BB)
• S-Comm SDN
• CDH Test Rack, FEDS, Flight Software GSE, NTGSE
• Single Board Computer
• NTGSE, Flight Software GSE, possible timing
  interface to CDH Test Rack
• Bulk Memory Card
• CDH Test Rack (for playback test)
• Ka DCDC card
• None
• Power Converter Card Low Power Switch Card
• CDH test rack (resistive loads for LPSC)

• CDH Subsystem Testability
• The Subsystem is required to verify built to
  requirements and validate that function works,
  but it must also be able to perform functional
  testing through out development and mitigate
  hardware, cost schedule risk.
• The approach that the Subsystem plans to employ
  to facilitate appropriate testing at all phases
  of development and to eliminate retro activities.
  Such as
• Detailed test procedures that encompass testing
  at BB, ETU and FLT designs, both at the card and
  box level.
• PDT designs cards from the start to employ
  testing at various stages of development.
• Inter subsystem communication for demands of test
  at spacecraft IT stage.
• Appropriate test points at the card level for
  testing.
• Sufficient test points at front panel to allow
  FPGA test/analysis, before opening the box.
• Branch level configuration software for card and
  FPGA designs to mitigate incorrect version loads.
  This ensures that test protocols are kept
  updated.

18
GSE Block Diagram
19
Status (1/3)

• The CDH Subsystem is presently at the end stages
  of Breadboard design for most cards and subsystem
  development.
• Identified RFAs still require closure.
• Some Interfaces still require clarification, plan
  in place and expect satisfactory closeout.
• Peer review for CDH Backplane still requires
  completion
• Certain documents still require project review
  and approval
• When these items are satisfactorily closed out
  the CDH Subsystem will be ready to proceed to
  Breadboard layout.
• All Bread Board parts have been selected by
  Subsystem PDT and confirmed by Parts Team, to
  have a path to migrate to flight acceptable
  parts.
• Devices/parts used in CDH designs have been
  reviewed by parts team and have received initial
  approval.
• Subsystem will work closely with Parts team to
  ensure completion of parts testing and screening.
• No parts issues are present to date.
• No Breadboard part is delivered later than 6/7/04
  (Kit Date)

20
Status (2/3)

• CDH Subsystem Doc DOC Status
• ICD 464CDH-ICD-0029 Preliminary
• REQUIREMENTS 464-CDH-REQ-0038 Submitted for
  formal review with CCR
• GSE REQUIREMENTS 464-CDH-REQ-0030 Preliminary
• Development Plan 464-CDH-PLAN-0028 Preliminary
• HSB ICD 464-CDH-ICD-0012 Preliminary
• Single Board Computer (SBC)
• SBC SOW 464-CDH-LEGL-0008 Baselined
• SBC Specification 464-CDH-SPEC-0012 Baselined
  
• cPCI Backplane
• cPCI ICD (J1 J2) 464-CDH-ICD-0032 Review
• cPCI REQ 464-CDH-REQ-0044 Review

21
Status (3/3)

• Status to date
• Boards designs have had Peer level Reviews
• Subsystem has had Subsystem level PDR
• Board circuit designs for Layout are complete
  pending RFA (Peer and PDR) completion.
• Major RFAs still in an open status are
• CDH system  RFA 15 MDM connector Harnessing
  Issues 
• Ka (and HSB)
• RFA's 8 34 Atmel Radiation concerns,
• RFA's 23,14,33,5,12 Resync issues (effect on
  BER) 
• SBC RFA's 4,25, 43 52 EEprom boot area lockout
  (may require change to RFP)
• DC DC Card RFA 17 31 Backplane capacitance and
  effect on in-rush 
• Comm Card RFA 12- 3.3V differential signal vs.
  5V for 422 
• BMC RFA 18 (radiation susceptibility of SDRAM
  not known)

22
Development Flow
Latest S/W Load GSE
PDR
BB Dev. Phase
Design
Fab
Test
Concept/Reqs. Review
BB mods. folded into ETU design
(sufficient to test/verify all H/W interfaces
functions)
Design Peer Review
Updated S/W Load
ETU Dev. Phase
Design
Fab
Test
Design Peer Review
Thermal Test
CDR
Systems Eng. Pre-Fab Review
ETU mods. Folded into Flight design Updated S/W
Load
Flight Dev. Phase
Design
Fab
Test
Systems Eng. Pre-Fab Review
Environmental Test Phase
Deliver to Spacecraft
EMI/EMC
Vibration
Thermal Vac
EMI/EMC Results Review
Vibration Results Review
Thermal Vac Results Review
23
CDH Schedule
CY 2003
CY 2004
CY 2005
CY 2006
CY 2007
CY 2008
Subsystem Element
Q4
Q1
Q2
Q3
Q4
3/04
2/08
4/08
5/07
5/04
2/05
8/03
4/8
MISSION MILESTONES
LAUNCH
SRR/ SCR
CR
CDR
ICR
PDR
PSR
PER
CDH Milestones
1/8/04
10/04
CDR
PDR
PSE SDN
BB
ETU
FLT
S-Band Comm SDN
BB
ETU
FLT
Backplane (cPCI)
BB
ETU
FLT
Cards
Ka-Band Card S-Band Card DC/DC Card SDN
Backplane Bulk Memory
BB
ETU
FLT
SBC
Award
CDH Module
Assembly, Test Closeout
Environmental Test
Spacecraft IT
1
2
3
4
Launch
24
Conclusion - Program Assessment

• The CDH Subsystem has a viable implementation
  plan.
• The Requirements and Documentation are in place
  and pending review completion
• The CDH Subsystem is adequately staffed and has
  sufficient resources to successfully proceed.
• Major milestones have been worked into Subsystem
  schedule and adequate slack before delivery to
  spacecraft has been integrated.
• Issues have been clearly itemized and identified.

25
SDO CDH MISSION PDRBACKUP SLIDES
26
Processing Element Resets
Reset Action BC/RT Register SDRAM FSW IMAGE Register
Power-On (POR) Resets All on BMC and SBC Cleared (RT mode) Initialize to zeros Cleared (EEPROM Image)
HW Cmd 3 Resets All on BMC and SBC Cleared (RT mode) Initialize to zeros Cleared (EEPROM Image)
HW Cmd 5 Resets SBC and partial BMC Set (BC mode) No Change No Change from last state
S/W Commanded Cold Start (via WD timer?) SBC Vendor specific BMC partial No Change from last state No Change No Change from last state
Watchdog Timer Reset SBC Vendor specific. BMC partial No Change from last state No Change No Change from last state
S/W Commanded Warm Start Does not reset hardware. Restarts FSW No Change from last state No Change No Change from last state
HW Cmd TBD Resets SBC and partial BMC No Change from last state No Change Set (PROM Image)
Note BMC functions reset during partial reset
1. cPCI target FPGA, 2. MIL-STD-1553
protocol chip, 3. SRAM/Sync Serial Port
(SSP)/1553 Control FPGA,
desirement??
27
Atmel 1355 Usage
AIA Instrument Electronics
AIA Interface Electronics
200 Mbps Link Rate lt 160 Mbps Data Rate
1355 Type 1-port Mode Protocol Managed
Remotely Active Qty 4 Inactive Qty
0 Redundancy None
1355 Type 1-port Mode Protocol Managed
Locally Active Qty 4 Inactive Qty 0 Redundancy
None
1355 Type 3-port Mode Transparent Managed
Locally Active Qty 1 Inactive Qty 1 Redundancy
per HSB ICD
10 Mbps Link Rate 0 Mbps Data Rate
Ka Comm
HMI Instrument Electronics
HMI Interface Electronics
200 Mbps Link Rate lt 160 Mbps Data Rate
100 Mbps Link Rate lt 55 Mbps Data Rate
1355 Type 3-port Mode Transparent Managed
Locally Active Qty 2 Inactive Qty 0 Redundancy
per HSB ICD
1355 Type 1-port Mode Protocol Managed
Remotely Active Qty 2 Inactive Qty
0 Redundancy None
1355 Type 1-port Mode Protocol Managed
Locally Active Qty 2 Inactive Qty 0 Redundancy
None
1355 Type 3-port Mode Transparent Managed
Locally Active Qty 1 Inactive Qty 1 Redundancy
per HSB ICD
10 Mbps Link Rate 0 Mbps Data Rate
10 Mbps Link Rate 0 Mbps Data Rate
EVE Instrument Electronics
EVE Interface Electronics
not 1355
not 1355
1355 Type 1-port Mode Transparent Managed
Locally Active Qty 1 Inactive Qty 1 Redundancy
per HSB ICD
Note Data Rate does not include 1335 control
characters (EOP1, EOP2, FCT, NULL)
28
HSB IM_PDU Context in CCSDS
IM_PDU is VCDU Insert Zone M_PDU
Ka
RF
Ka
Instr
29
Functional Signal Distribution
AirBorn Connector
DGND
DGND
PAT Passive Analog TLM
AAT Active Analog TLM AGND Analog
Ground DGND Digital Ground