Software Defined Radio

1
Software Defined Radio Cognitive Radio
Implementation Initiatives

• KRISHNA KUMAR S.
• Centre for Development of Advanced Computing
• krishku_at_cdac.in

2
C-DAC
A National Centre of Excellence and premier R
D institution under DIT, MCIT, Govt. of
India involved in the design, development and
deployment of Electronics IT- based solutions
for human advancement
3

• 10 Locations
• 14 Centres
• 3000 members

4
Broadcast Communications _at_ C-DAC
TETRA
MANET CR CNM NG WF SDR
AM/FM Radios Television Alpha Numeric
Information Displays CCTV Cameras Monitors Direct
Reception System Multifunction mono/stereo Audio
Consoles CD Players Equalizers Monitoring
Amplifiers Digital Audio Work Stations
VoIP
Digital Audio
Software Defined Radio
Networking
TETRA-WiMax
1990 2000
2010
2015
5
C-DAC SDR programme road map
Handheld
SDR Demos- 2 SCA WFS
SDR-NC
SDR Manpack
CR
C-DAC SDR proposal
Study Report
1st SDR Project
SDR PoC
2004
2006
2007
2008
2010/11
2012
2012
2013
2009
DIT
DIT
DIT
DIT
C-DAC
SDR-Demo
DIT
C-DAC
NAVY
6
recent/current projects in SDR/CR

• SDR for Naval Communication (DRDO)
• SDR Manpack (DIT)
• SDR Handheld (Core funding)
• Cognitive Radio Networks (DIT)
• jointly with IISc.
• Next Generation Waveforms for SDR
• Related projects
• Mobile Adhoc NETworks (MANET)
• Autonomic Network Management Systems (ANMS)

7
the PoC SDR lab model

• Demonstrated re-configurablity with two SCA
  compliant waveforms
• TETRA UHF band Military
• Legacy FM Radio (VHF band) Clear Mode

8
SDR manpack product perspective
9
agenda

• introduction
• SDR architecture
• SDR waveforms
• from SDR to CR
• Spectrum Sensing Engine
• application scenarios
• conclusions

10
Software Defined Radio

• a radio in which some or all of the radios
• operating functions are implemented through
  modifiable software or firmware

11
SDR Platform

• Consists of
• Hardware,
• Firmware,
• Operating system
• Middleware
• Takes different personalities, defined by the
  waveform that is loaded

12
SDR platform architecture
13
RF transceiver
14
Hopping Synthesizer
15
Harmonic Filter Bank
16
Baseband Boards
17
agenda

• introduction
• SDR architecture
• SDR waveforms
• from SDR to CR
• Spectrum Sensing Engine
• application scenarios
• conclusions

18
Waveform Definition

• From http//www.wirelessinnovation.org/Introductio
  n_to_SDR
• The set of transformations applied to information
  to be transmitted and the corresponding set of
  transformations to convert received signals back
  to their information content.
• Representation of a signal in space
• The representation of transmitted RF signal plus
  optional additional radio functions up to and
  including all network layers.

19
Waveform

• Can be visualized at different levels
• Architecture
• Conceptual entity
• Defines and abstracts the waveform functions
• Almost independent of the platform specifics
• Implementation
• Physical realization of architecture
• Closely related to platform

20
Waveform Architecture design

• What it is?
• What it is not?

21
Architecture design process
Candidate Architecture
SIMULATION
Final Architecture
22
Waveform Implementation

• Physical realization of architecture
• Closely related to platform
• Implementer should know
• Overall platform architecture
• Availability of Computing elements
• GPP, DSP, FPGA
• Other configurable resources
• clocks, vca, vco, tunable filters etc.

23
Task Partitioning among CEs
GPP
DSP
FPGA

• PHY Bit level processing
• Symbol rate processing
• Soft real-time numerically intensive tasks e.g.
  channel estimation

• Ideally all hard real time PHY functions
• Tasks best implemented using parallel
  architecture
• Symbol rate processing for wideband systems

• Signaling and control
• Higher layer and MAC functions

RULES OF THUMB
24
What devices in a given SDR?

• Device architectures are being upgraded
  constantly
• New FPGAs realize DSP functions using specific
  architectures
• New DSPs use hardware accelerators to implement
  hard real time tasks
• GPP performance too scales up
• Blurred boundaries! Vanishing boundaries?
• Platform designer priorities do matter

25
Portability Re-configurability

• Probably the most important features of SDR
• Waveform should be portable across platforms a
  statement to be qualified
• Waveform should be able to configure and control
  platform resources
• Ensured by proper design and implementation of
  Waveform and Platform
• May result in sub-optimal implementation
• but thats okay! in most cases

26
Application Program Interfaces

• Key enabler in ensuring portability
  re-configurability
• Abstracts low level functions
• Platform provider to facilitate platform
  abstraction through APIs
• Waveform implementer to use APIs to access
  platform features

27
GPP DSP APIs

• GPP API calls are typically POSIX calls
• DSP API calls are C-function calls
• API implemented as a library
• API to be used while building DSP image

28
RF APIs

• To abstract Radio functions
• Tuning LO
• Configure Tx. DAC
• Configure AGC
• Etc.
• API calls are pre-defined messages
• Processed and executed by a dedicated controller

29
FPGA Wrapper

• Equivalent of API for FPGA
• Wrapper defines the platform logic
• Waveform logic defines the (part of) PHY signal
  processing
• Waveform logic to be integrated with wrapper

30
FPGA Architecture
FPGA IO Ring
DSP
TOP module
RF Control
SPI Signals
SPI Glue
ADC FIFO
Waveform Logic
14 bit
ADC
EMIF

EMIF Glue
DAC FIFO
DAC
16 bit
GPIO (Push Buttons, LEDs, DIP Switches, GPIO
Headers)
McBSP
McBSP Glue
Interrupt 1
Interrupt 2
uPP
uPP Glue
UART Glue
UART Port
31
FPGA model based design

• To design waveform signal processing
• Can be done in a graphical way
• Designer need not no low-level architecture of
  the device
• Can be used jointly with Matlab/Simulink or
  similar simulation environments

32
FPGA model based design tools

• Xilinx - System Generator
• Altera - DSP Builder
• Actel - Synplify
• Lattice - ispLever DSP
• Agilent system view VHDL code generation

33
FPGA integration with wrapper

• Combine the HDL source level
• Combine the wrapper source with waveform netlist
• Similar to adding a library
• Combine at bitmap level
• Wrapper logic implemented in advance
• Waveform logic added using partial reconfiguration

34
agenda

• introduction
• SDR architecture
• SDR waveforms
• from SDR to CR
• Spectrum Sensing Engine
• application scenarios
• conclusions

35
from SDR to CR

• A natural evolution
• CR, by nature, has to be an SDR
• but,
• an SDR with certain specific fetures.

36
CR additional requirements

• A truly wideband radio front end
• Support for White/Gray space detection
• Spectrum sensing - hardware software
• Geo-location and Database
• IEEE 802.22
• Dynamic Spectrum Management
• Channel Bandwidth allocation
• Rate adaptation Tx power control

37
from SDR to CR concerns

• Algorithm complexities of course
• A truly wideband radio front end
• Tx side RF Power amps
• Rx side wide band sensing
• AD/DA conversion bottle-necks
• Noise, sensitivity, interference protection, SFDR

38
agenda

• introduction
• SDR architecture
• SDR waveforms
• From SDR to CR
• Spectrum Sensing Engine design
  implementation
• application scenarios
• conclusions

39
Primary Signal Details

• Primary Terrestrial analog TV txn in India
• System CCIR system B,G PAL
• Bands
• Band II VHF 174 to 225 MHz
• Band IV UHF 470 to 582 MHz
• Channel BW 8 MHz

40
Requirements

• Incumbent Detection Threshold
• -94 dBm (measured at peak of sync)
• Channel Detection Time
• lt2 sec per channel
• Detection Performance
• Probability of Detection gt90 at False Alarm
  rate of lt 10
• Guided by IEEE 802.22 WRAN WG interim
  recommendations

41
Platform - Lyrtech SFF SDR
42
(No Transcript)
43
From SS Algorithm to SS Engine (from recipe to
dish)

• Study of algorithm
• Study of hardware architecture
• Designing software architecture
• Optimal partitioning of algorithm
• Model based design / C-program development
• Fixed point considerations
• dynamic range, bit growth, over/under-run,
  truncation error
• Defining and realizing interfaces
• Debugging, testing and optimization

44
Detection Scheme

• Pre-processing/Feature extraction stage
• Extracts the spectrum around the picture carrier
• Energy Detection stage
• Computes the energy around the pictures carrier

45
(No Transcript)
46
Pre-Processing
to sensing algorithm BW 100kHz 500 Ksps 32 bits
Decimating filter stages
Digital IF BW 8MHz 125 Msps 14 bits
DDS _at_ 30MHz
47
Implementation

• Implemented in the FPGA part (Virtex 4)
• Design using Simulink / System generator
• Model based design approach
• Fixed point implementation
• Word-length selection
• bit growth
• truncation error
• resource utilization

48
Energy Detection

• N samples x B buffers
• Gives the adavntage of averaging
• Reduces the FFT implementation complexity

49
Implementation

• Implemented in the DSP (TMS320C64X)
• Code developed in C language
• Debugged using Code Composer Studio XDS560 ICE
  
• A fixed point implementation
• Word-lengths selection

50
User Interface
51
(No Transcript)
52
Lab Setup
53
Test Settings

• Picture carrier 67.25MHz
• Channel Bandwidth 8MHz
• Video pattern White
• Sensing duration 20.4 ms
• Sampling rate 125Msps
• Ensemble size 1e5
• SNR values -30dB, -27dB, -24dB

54
PAPR for ATV
Courtesy Martyn J. Horspool, Analog-to-digital
Upgradeable Transmitters For the Worldwide
Market, Harris Corporation
55
Results
56
Results

• System meets the false alarm/miss detection
  performance at -27 dB SNR
• Highly encouraging result
• Enough margin to accommodate large scale fading
• Caveat This is only a lab measurement

57
agenda

• introduction
• SDR architecture
• SDR waveforms
• from SDR to CR
• Spectrum Sensing Engine
• application scenarios
• conclusions

58
application areas

• Military
• PMR (public safety, police, paramilitary)
• Disaster management
• Commercial Cellular (Base Stations)
• Rural broadband access
• IEEE 802.22 system adaptaion
• Tele-Medicine

59
acknowledgements

• Simon Zachariah
• Beena K. T.
• S. Sagar
• Chandra R. Murthy
• Shine K. P.
• Satheesh Kumar S.

60
Questions ??

• thank you