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EBB 323 Semiconductor Fabrication Technology

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EBB 323 Semiconductor Fabrication Technology Epitaxy Dr Khairunisak Abdul Razak Room 2.16 School of Material and Mineral Resources Engineering Universiti Sains Malaysia – PowerPoint PPT presentation

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Title: EBB 323 Semiconductor Fabrication Technology


1
EBB 323 Semiconductor Fabrication Technology
Epitaxy
Dr Khairunisak Abdul Razak Room 2.16 School of
Material and Mineral Resources Engineering Univers
iti Sains Malaysia khairunisak_at_eng.usm.my
2
Topic outcomes
  • At the end of this topic, students should be able
    to
  • Name 2 types of epitaxy
  • Describe the applications of epitaxial layers
  • Explain techniques to produce epitaxial layers
  • Describe structure and defects in epitaxial
    layers

3
Introduction
  • Epitaxy comes from Greek words
  • Epi upon
  • Taxis ordered
  • Epitaxial growth single crystal growth of a
    material in which a substrate serve as a seed
  • 2 types of epitaxy
  • Homoepitaxy material is grown epitaxially on a
    substrate of the same material. E.g. grow of Si
    on Si substrate
  • Heteroepitaxy a layer grown on a chemically
    different substrate. E.g. Si growth on sapphire
  • Similar crystal structures of the layer and the
    substrate, BUT
  • The shift of composition causes difference in
    lattice parameters
  • Limit the ability to produce epitaxial layers of
    dissimilar materials

4
Film deposited on a lt111gt oriented wafer ?lt111gt
orientation
The presence of SiO2 Layer cause depositing atoms
have no structure?polysilicon
Epitaxial and polysilicon film growth
5
Applications of epitaxial layers
  • Discrete and power devices
  • Integrated circuits
  • Epitaxy for MOS devices

6
1. Discrete and power devices
  • Technology change junction transistors ?
    diffused planar structure
  • Requires a material structure that are not
    achieved by diffusion of dopants from the surface
  • Si epitaxy was developed to enhance the
    electrical performance of discrete bipolar
    transistors
  • Breakdown voltage of the discrete transistor was
    limited by the field avalanche breakdown of the
    substrate material
  • Use higher resistivity substrates produced higher
    breakdown voltages but increased collector series
    resistance
  • Structure needed thin, lightly doped and single
    crystal layer of high perfection upon more
    heavily doped Si substrate
  • But, the use of a more heavily doped substrate
    reduces the collector series resistance while the
    base-collector breakdown voltage is governed by
    the lighter doping in the near surface region

7
  • Epitaxial deposition of a lightly doped P
    epitaxial layer on a N substrate make the
    desired properties are achievable
  • Epitaxial grows also allows accurate control of
    doping levels and advantages which arises from a
    generally low oxygen and carbon levels in
    epitaxial layer
  • Epitaxial technique was developed to 2 and 3
    layers epitaxial structure
  • For lightly doped area of collector
  • Based region was also grown epitaxially
  • E.g. of multilayer structures Si-Controlled
    Rectifier (SCR), Triac, high voltage or high
    power discrete products

8
Mesa discrete transistor fabricated in an
epitaxial layer on a heavily doped N substrate
9
Transistors
Diodes
10
2. Integrated circuit (IC)
  • Development of planar bipolar IC caused the
    requirement for devices built on the same
    substrate to be electrically isolated
  • The use of opposite typed substrate and epitaxial
    layer met part of the requirement
  • Device isolation was completed by the diffusion
    of isolation region through the epitaxial layer
    to contact the substrate between active areas
  • In planar bipolar circuits, common to employ a
    heavily doped diffused (or implanted) region
    under the transistor
  • Usually called buried layer or DUF for
    diffusion under film
  • The buried layer
  • serves to lower the lateral series resistance
    between collector area below the emitter and the
    collector contact
  • produce uniform planar operation of the emitter,
    avoiding current crowding which leads to hot
    spots near edges of the emitter

11
Integrated circuits
12
(a) A junction isolated bipolar device fabricated
as part of an integrated circuit using a buried
layer subcollector and a lightly doped
n-epitaxial layer
(b) An N-Well CMOS structure fabricated in a
lightly doped p-epitaxial layer
13
3. Epitaxy for MOS devices
  • Unipolar devices such as junction field-effect
    transistors (JFETs), VMOS, DRAMs technology also
    use epitaxial structures
  • VLSI CMOS (complimentary metal-oxide-semiconductor
    ) devices have been built in thin (3-8 micron)
    lightly doped epitaxial layers on heavily doped
    substrates of the same type (N or P)
  • That epitaxial structure reduces the latch up
    of high density CMOS IC by reducing the unwanted
    interaction of closely spaced devices

14
Advantages of epitaxy
  • Ability to place a lightly oppositely doped
    region over a heavily doped region
  • Ability to contour and tailor the doping profile
    in ways not possible using diffusion or
    implantation alone
  • Provide a layer of oxygen free material that is
    also contained low carbon

15
Techniques for silicon epitaxy
  • Chemical Vapour Deposition (CVD)
  • Molecular Beam Epitaxy (MEB)
  • Liquid Phase Epitaxy (LPE)
  • Solid phase regrowth

16
1. Chemical Vapour Deposition (CVD)
  • The most common technique in Si epitaxy
  • In the CVD technique
  • Si substrate is heated in a chamber sufficient
    heat to allow the depositing Si atoms to move
    into position to
  • Reactive Si containing gaseous compounds are
    introduced
  • Gaseous react on the hot surface of the substrate
    and deposit a Si layer
  • The deposit will take on Si substrate structure
    if the substrate is atomically clean and the
    temperature is sufficient for atoms to have
    surface mobility

17
Schematic drawing of a simple horizontal flow,
cold wall, CVD reactor
18
  • Schematic CVD reactor geometries for
  • True vertical reactor
  • Classic horizontal flow reactor
  • Modified vertical (or pancake) reactor
  • Downflow cylinder reactor

19
CVD processes and products
20
CVD for silicon devices
21
CVD reactions
  • Pyrolysis chemical reaction is driven by heat
    alone, e.g. silane decomposes with heating
  • SiH4 ? Si 2H2
  • Reduction chemical reaction by reacting a
    molecule with hydrogen, e.g. silicon
    tetrachloride- reduction in hydrogen ambient to
    form solid silicon
  • SiCl4 2H2 ? Si 4HCl
  • Oxidation chemical reaction of an atom or
    molecule with oxygen, e.g. SiH4 decomposes at
    lower temperature
  • SiH4 O2 ? SiO2 2H2
  • Nitridation chemical process of forming silicon
    nitride by exposing Si wafer to nitrogen at high
    temperature e.g. SiH2Cl2 readily decomposes at
    1050?C
  • 3SiH2Cl2 4NH3 ? Si3N4 pH 6H2

22
CVD
23
CVD film growth steps
  • Nucleation
  • Dependent on substrate quality
  • Occurs at first few atoms or molecules deposit on
    a surface
  • Nuclei growth
  • Atoms or molecules form islands that grow into
    larger islands
  • Island coalescence
  • The islands spread , and coalescing into a
    continuous film
  • This is the transition stage of the film growth,
    thickness several hundreds Angstroms
  • Transition region film possesses different
    chemical and physical properties for thicker bulk
    film
  • Bulk growth
  • Bulk growth begins after transition film is formed

24
CVD film growth steps
Types of film structure
Amorphous
Polycrystalline
Single crystal
Basic CVD subsystem
25
  • CVD Process steps
  • Pre-clean remove particulates and mobile ionic
    contaminants
  • Deposition
  • Evaluation thickness, step coverage, purity,
    cleanliness and composition

Pre-clean
Deposition
Evaluation
Load wafer into chamber, inert atmosphere
Introduce chemical vapour
Remove vapour
Heat
Flush excess chemical vapour source
26
2. Molecular Bean Epitaxy (MBE)
  • Uses an evaporation method
  • MBE is carried out at a lower temperature than
    1000-1200?C (typical CVD temperature)
  • Reduces outdiffusion of local areas of dopant
    diffused into substrates and reduce autodoping
    which is unintentionally transfer of dopant into
    epitaxial layer
  • MBE is favourable
  • preparation of sub-micron thickness epitaxial
    layers or
  • high frequency devices requiring hyper-abrupt
    transition in the doping concentration between
    the epitaxial layer and the substrate

27
  • In MBE,
  • Si and dopant(s) are evaporated in an ultra high
    vacuum (UHV) chamber
  • The evaporated atoms are transported at
    relatively high velocity in a straight line from
    the source to the substrate
  • They condense on the low temperature substrate
  • The condensed atoms of Si or dopant will diffuse
    on the surface until they reach a low energy site
    that they fit well the atomic structure of the
    surface
  • The adatom then bonds in that low energy site,
    extending the underlying crystal by a vapour to
    solid phase crystal growth
  • Usual temperature range of the substrate is
    400-800?C. Higher than 800?C is possible but it
    will increase outdiffusion or lateral diffusion
    of dopants in the substrate

28
Schematic drawing of a molecular beam epitaxial
system
29
  • Insitu cleaning of the substrate
  • Can be done by high temperature bake at
    1000-1250?C for several minutes under high vacuum
    to decompose the native surface oxide and to
    remove other surface contaminants
  • Other technique is by using a low energy beam of
    inert gas to sputter clean the substrate
  • Difficult to remove carbon but will decrease at
    the surface by diffusion into the substrate
    during short anneal at 800-900?C
  • Wider range of dopants for MBE than CVD epitaxy
  • Typical dopants Antimony, Sb (N-type), aluminum,
    Al or gallium (Ga) for P-type
  • N-type dopant As and P, evaporate rapidly even
    at 200?C. Difficult to control
  • P-type dopant Boron, evaporate slowly even at
    1300?C

30
Schematic drawing of a multiple chamber MBE system
31
MBE Equipment
32
Liquid Phase Epitaxy (LPE)
  • LPE technique is widely used for preparation of
    epitaxial layers on compound semiconductors and
    for magnetic bubble memory films on garnet
    substrate
  • In films growth by LPE from solution melts, low
    cooling rates, when the surface reaction (growth)
  • Kinetics are rapid compare to the mass transport
    of Si to the seed, epitaxial layer thickness will
    vary in proportion to the temperature drop
  • Increase cooling rates, mass transport rate will
    increase and the growth rate will increase with
    cooling rate until growth rate becomes limited by
    surface reaction kinetics

33
  • Growth rate increases with cooling rate up to
    about 1 degree/min while growth rate above 2
    degree/min occurred under kinetically limited
    conditions

LPE growth rate increasing with cooling rate up
to about 1 micron per minute
34
Schematic drawing of a typical silicon liquid
phase epitaxy (LPE)
35
  • Fabrication sequence for a vertical channel field
    effect transistor
  • N and N epitaxial structure can be built using
    liquid or vapour phase epitaxial growth
  • Preferential etching can be used to open areas
    part way through the N type epitaxial layer
  • In this figure, LPE is used to fill the etched
    out gate areas which control current flow
    vertically from the top side source to the N
    substrate drain region

Schematic of fabrication steps in the fabrication
vertical field effect transistors by etch and LPE
refill techniques
36
4. Solid Phase Re-growth
  • Re-growth of amorphous layers
  • Surface layers subjected to high dose ion
    implants are in amorphous structure due to the
    heavy damage inflicted on the lattice as the
    energetic ions are absorbed
  • Annealing above 600?C ? amorphous layer
    re-crystallize
  • Re-crystallisation occurs from interface moves
    toward the surface and results in solid phase
    epitaxial re-growth

37
  • Re-crystallisation of thin films
  • Involves re-crystallisation of a deposited
    amorphous or polysilicon film
  • Si film is deposited on a Si substrate or more
    commonly SiO2 ? heated using a strip heater
    passed over the surface or by a scanned pulsed
    laser to crystallise the film to single crystal
    or large grain polysilicon
  • This fabrication technique is used to produce a
    stacked n-channel device in re-crystallised
    polysilicon on a thermally grown or deposited
    oxide
  • Oriented epitaxial growth can be obtained by
    making series of holes in the oxide to allow
    points of contact between the underlying
    substrate and the deposited polysilicon
  • The contact points become seeds areas for
    establishing re-growth orientation

38
Re-crystallisation solid phase epitaxy using a
moving strip heater
A stacked MOS structure over an insulating oxide
fabricated in a re-crystallised polysilicon layer
39
Structure and defects in epitaxial layer
  • Surface morphology of Silicon epitaxial deposits
    is affected by growth and substrate parameters
  • Growth parameters
  • Temperature
  • Pressure
  • Concentration of Si containing gas
  • Cl H2 ratio
  • Substrates parameters
  • Substrate orientation
  • Defects in the substrate
  • Contaminants on the surface of the substrate

40
Typical defects in epitaxial layers
  • Substrate orientation effects
  • Spikes and epitaxial stacking faults
  • Hillocks and pyramids in epitaxial layers
  • Dislocations and slip
  • Microprecipitates (S-pits)

41
1. Substrate orientation effect
  • Growth of smooth epitaxial films can be obtained
    on (100) and (110) oriented Si substrates
  • Epitaxial growth on substrate surface on oriented
    on (111) plane results in facetted alligator
    skin surface
  • (111) surfaces contain no atomic steps to provide
    a density of growth sites
  • Without atomic steps, the growth produces
    pyramids and terraces
  • Misorientation of the surface by ? 0.5 degree
    introduces a sufficient density of steps for
    growth of smooth planar films

42
2. Spikes and epitaxial stacking faults
  • Growth spike
  • Originate from Si particle on the surface not
    removed by the pre-epitaxial cleaning process
  • Si Chips may expose faster growing crystal planes
    than the plane of the substrate
  • Chips nucleate and produce polysilicon nodule.
    The chips then protrude above the substrates
    surface into a region of richer supply of gaseous
    reactants
  • Results in nodule grows at 2-10 times the rate of
    epitaxial film on the substrate.
  • May be removed mechanically before the next step
    but will leave a region unusable for functional
    materials

43
  • Epitaxial stacking faults
  • Crystallographic in nature and arise from defects
    in atomic arrangement during film growth
  • Could result from an extra atomic layer
    (extrinsic fault) or a missing atomic layer
    (intrinsic fault) along 111 type plane

44
Epitaxial growth spike
Stacking fault on lt111gt Si
45
3. Hillocks and pyramids in epitaxial layers
  • Hillocks Small oval mounds on the surface of the
    epitaxial
  • Pyramids Faceted regions on the epitaxial
    surface
  • Density of hillocks and pyramids is dependent on
    growth parameters such as type and concentration
    of Si source and deposition temperature

46
4. Dislocations and slip
  • Non-uniform heating of a substrate results in
    non-uniform thermal expansion of the substrate
    which produces elastic stresses
  • The thermal stress can cause bowing which may
    lift the edge of the substrate away from the
    substrate in response to the thermal stress
  • At lower temperature (lt 900?C) the yield point of
    the Si lattice is sufficiently high that the
    substrate behaves elastically. During cooling,
    the thermal stress is removed and the substrate
    returns to its original shape
  • If the stress exceeds a critical values, the
    substrate will yield plastically ? occurs due to
    generation and motion of dislocations which are
    atomic level line defects which glide along slip
    planes of the crystal

47
  • The passage of one dislocation offsets the
    material above and below the slip plane by a unit
    known as Bergers vector of the dislocations
  • Dislocations normally propagate from near the
    edge of the substrate (highest stress), and glide
    towards the centre of the substrate and produce
    plastic deformation of the substrate which
    relieves the thermal stress
  • Dislocation motions is slow because dislocation
    moves to a region of lower shear stress
  • The continuous slow motion of the dislocations
    produces creep deformation of the crystal
  • Device impact from slip normally comes from rapid
    pipe diffusion of dopant along the core of the
    dislocations

48
Typical wafer edge slip as a result of excessive
within wafer temperature gradients during heating
or during epitaxial film growth
Crystal slip
49
5. Microprecipitates (S-pits)
  • Microprecipitates may come from metallic
    elements such as copper, nickel, iron and
    chromium
  • This is due to their solubility in Si at high
    temperatures and fast diffusion rates through the
    Si
  • The metal contaminants may exist in the starting
    substrates or being pick up during handling in
    the loading operation or from metal parts or
    susceptors within the epitaxial reactor itself

50
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