Graduate Computer Architecture I

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Graduate Computer Architecture I

• Lecture 15 Intro to Reconfigurable Devices

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Quick Review Digital Logic
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Typical Circuit (Full-Adder)
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NAND
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Full-Adder Using NAND
A B C
S
C
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VLSI Layout of NAND Full-Adder
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Full-Adder Using Array of Logics
S
C
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Programmable Logic (PLA/PAL/PLD)
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More Complex Programmable Logic
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Programmable Logic
Inexpensive One-time Programmable Devices
BURN it once and use!
Complex Programmable Logic Devices
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Full Adder Using Memory
8 by 2-bit Memory
3bit Address Concat(C,A,B)
Addr
2bit Data Concat(S,C)
Data
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Simple Wire Switch (4x4 Crossbar)
Input Ports
Output Ports
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Field Programmable Gate Array
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Logic Block (Xilinx Virtex 4000)
SRAM based Logic (4 input Look-up-table)
Registers
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FPGA Architecture
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Design Flow
DESIGN ENTRY
CORE GENERATION
RTL HDL EDITING
RTL HDL-CORE SIMULATION
SYNTHESIS
IMPLEMENTATION
TIMING SIMULATION
FPGA PROGRAMMING IN-CIRCUIT TEST
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HDL Design Flow
Accessed within HDL Editor
DESIGN WIZARD
LANGUAGE ASSISTANT
HDL EDITOR
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IP Core Generation
Select core and specify input parameters
CORE GENERATOR
EDIF netlist for core_name
Other core_name files
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Functional Simulation
Set Up and Map work Library
RTL HDL Files
Testbench HDL Files
Compile HDL Files
Test Inputs or Force Files
MODELSIM
Functional Simulate
Waveforms or List Files
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Synthesis
All HDL Files
Edit FPGA Express Synthesis Constraints
Select Top Level
Synthesis/Implement-ation Constraints
Select Target Device
FPGA EXPRESS
Synthesize
Gate/Primitive Netlist Files (EDIF or XNF)
Synthesis Report Files
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Implementation
Gate/Primitive Netlist Files (XNF or EDN)
Netlist Translation
XILINX DESIGN MANAGER
Map
Place Route
Model Extraction
Timing Model Gen
Create Bitstream
HDL or EDIF for Implemented Design
Standard Delay Format File
BIT File
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Timing Simulation
HDL or EDIF for Implemented Design
Standard Delay Format File
Set Up and Map work Directory
Testbench HDL Files
Compile HDL Files
MODELSIM
Test Inputs, Force Files
Compiled HDL
HDL Simulate
Waveforms or List Files
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Programming FPGA
Bit File
Input Byte
GXSLOAD
GXSPORT
FPGA
Other Inputs
Outputs
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Emergence of FPGA

• Great for Prototyping and Testing
• Enable logic verification without high cost of
  fab
• Reprogrammable ? Research and Education
• Meets most computational requirements
• Options for transferring design to ASIC
• Technology Advances
• Huge FPGAs are available
• Up to 200,000 Logic Units
• Above clocking rate of 500 MHz
• Competitive Pricing

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System on Chip (SoC)

• Large Embedded Memories
• Up 10 Megabits of on-chip memories (Virtex 4)
• High bandwidth and reconfigurable
• Processor IP Cores
• Tons of Soft Processor Cores (some open source)
• Embedded Processor Cores
• PowerPC, Nios RISC, and etc. 450 MHz
• Simple Digital Signal Processing Cores
• Up to 512 DSPs on Virtex 4
• Interconnects
• High speed network I/O (10Gbps)
• Built-in Ethernet MACs (Soft/Hard Core)
• Security
• Embedded 256-bit AES Encryption

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Computational Density
Higher number means greater efficiency
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Potential Advantages of FPGAs
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Summary

• Rapidly changing platform
• Ten thousand times in silicon chip capacity
• Cost did not increase that much
• Same designs
• Von Neuman architecture time-multiplexes
• Old processor designs, only smaller
• Not much innovations
• Programmable SW/HW Platforms
• General Computing Systems do not have to look
  like traditional processors
• Future?