Introduction to Nano-Device Research in HKUST

1
Introduction to Nano-Device Research in HKUST

• Mansun Chan
• Professor, Dept. of ECE, HKUST

2
Major Projects

• Active Projects
• Nano-Transistor Fabrication and Modeling
• Multigate MOSFET modeling
• Nano-Biosensors for DNA detection and living cell
  monitoring
• Phase-Change-Memory Design and Modeling
• Low temperature semiconductor devices (ZnO,
  AlZnO)
• Energy efficient CMOS image sensors
• Power Management Circuits

3
Nano-Transistor Fabrication

• Double-Gate MOSFETs Fabrication

4
Nano-Transistor Fabrication

• 3-D Stacked Transistors

Vout Vin Vdd Vss
SOI film
G
PMOS
D
S
G
BOX
D
S
NMOS
Silicon base
Silicon base
Cross-section of the 3-D Inverter
5
Nano-Transistor Fabrication

• Stacked Nano-Transistors

6
Nano-Transistor Fabrication

• Nanowire Formation

7
Nano-Transistor Fabrication

• Transistor Characteristics

Diameter 10-50nm Lg250nm SS
62mV/dec Ion/Ioff gt 108 tox6nm of nanowires
3 Ion 1001mA/mm
8
Device Modeling

• BSIM3/BSIM4
• A member of the BSIM team at UC Berkeley
• The industrial standard and most widely used
  MOSFET model implemented in all commercial
  simulators
• Poisson and drift/diffusion based Model
• BSIMSOI
• Was first developed at HKUST and later imported
  to UC Berkeleys platform
• The current industrial standard

9
Device Modeling

• Multi-gate MOSFET Modeling
• Initiated Multi-gate MOSFET modeling work at UC
  Berkeley
• Team up with Peking University to derive more
  exact solution to the Poissons equations under
  more complicated boundary conditions
• Team up with researchers in Asia (Japan, Korea,
  Mainland China, HK) to develop a common modeling
  platform for advanced devices (received a NEDO
  grant of JPY70,000,000)

10
Device Modeling

• Example
• Nanowire transistor with doping
• SOI MOSFETs

11
Device Modeling

• Boundary conditions
• intermediate variables (charge, carrier,
  potential)
• ultra-thin body
• nanowire
• double-gate (symmetric/asymmetric/independent
  gate)
• doping
• quantum effects
• transport model (drift/diffusion versus
  scattering)
• continuity between different regions

12
Device Modeling

• Our Publications (Journal)

• J. He et. al., A Surface Potential-Based
  Non-Charge-Sheet Core Model for Undoped
  Surrounding-Gate MOSFETs, Journal of
  Semiconductors, Vol.30, No.2, pp.024001-1-024001-4
  , February 2009
• F. Liu et. al., A charge-based compact model for
  predicting the currentvoltage and
  capacitancevoltage characteristics of heavily
  doped cylindrical surrounding-gate MOSFETs,
  Solid-State Electronics, Vol. 53, Issue 1, pp.
  49-53, January 2009
• F. Liu, et. al., "A Non-Charge-Sheet Analytic
  Model for Symmetric Double-gate MOSEFTs with
  Smooth Transition Between Partially- and Fully-
  Depleted Operation Modes", IEEE Trans. on
  Electron Devices, Vol. 55, No. 12, pp. 3494-3502,
  December 2008
• J. Yang, et. al., "A Compact Model of
  Silicon-Based Nanowire MOSFETs for Circuit
  Simulation and Design", IEEE Trans. on Electron
  Devices, Vol. 55, No. 11, pp. 2898-2906, November
  2008
• F. Liu, et. al., A Charge-Based Model for
  Long-Channel Cylindrical Surrounding-Gate MOSFETs
  From Intrinsic Channel to Heavily Doped Body,
  IEEE Trans. on Electron Devices, Vol. 55, No. 8,
  pp. 2187-2194, August 2008
• F. Liu, et. al., "Generic Carrier-Based Core
  Model for Undoped Four-Terminal Double Gate
  MOSFETs Valid for Symmetric, Asymmetric and
  Independent Gate Operation Modes ", IEEE
  Transactions on Electron Devices, Vol. 55, No. 3,
  pp. 816-826, March 2008
• J.-F. Gong et. al., "An Explicit
  Surface-Potential-Based Model for Undoped
  Double-Gate MOSFETs", Solid-State Electronics,
  Vol. 52, Issue 2, pp. 282-288, February 2008
• J. He, et. al., "An Explicit Carrier-Based
  Compact Model for Nanowirre Surrounding-Gate
  MOSFET Simulation", Molecular Simulation, Vol.
  34, No. 1, pp. 81-87, January 2008
• J. He, et. al., A Unified Carrier-Based Model
  for Undoped Symmetric Double-Gate and
  Surrounding-Gate MOSFETs, Semiconductor Science
  and Technology, Vol. 22, pp. 1312-1316, October
  2007.
• J. He, et. al., A Carrier- Based Approach for
  Compact Modeling of the Long-Channel Undoped
  Symmetric Double-Gate MOSFETs, IEEE Trans. on
  Electron Devices, Vol. 54, No. 5, pp. 1203-1209,
  May 2007
• J. He, et. al., An Explicit CurrentVoltage
  Model for Undoped Double-Gate MOSFETs Based on
  Accurate Yet Analytic Approximation to the
  Carrier Concentration, Solid-State Electronics,
  Vol. 51, Issue 1, pp. 179-185, January 2007
• J. He, et. al., "A Physics-Based Analytic
  Solution to the MOSFET Surface Potential From
  Accumulation to Strong-Inversion Region, IEEE
  Trans. on Electron Devices, Vol. 53, No. 9, pp.
  2008-2016, September 2006
• J. He, et. al., "An Analytic Model to Account for
  Quantum-Mechanical Effects of MOSFETs Using a
  Parabolic Potential Well Approximation, IEEE
  Trans. on Electron Devices, Vol. 53, No. 9, pp.
  2082-2090, September 2006
• J. He, et. al., "A Carrier-Based DCIV Model for
  Long Channel Undoped Cylindrical Surrounding-Gate
  MOSFETs", Solid-State Electronics, Vol. 50, Issue
  3, pp. 416-421, March 2006
• J. He, et. al., "A continuous analytic IV model
  for long-channel undoped ultra-thin-body
  silicon-on-insulator (UTB-SOI) MOSFETs from a
  carrier-based approach", Semiconductor Science
  and Technology, Vol. 21, No. 1, pp. 261-266,
  January 2006

13
Phase-Change Memory

• Phase change material
• Ge2Sb2Te5 (GST), Sb2Te3 with N-doping (STN),
  Doped GeSb
• chalcogenide materials are alloys with a group VI
  element (usually combined with IV and V group
  elements)
• certain alloys containing one or more group VI
  elements (Chalcogenides) exhibit reversible
  transition between the disordered and ordered
  atomic structure

1. Y.C.Chen et al, Ultra-Thin Phase-Change
Bridge Memory Device Using GeSb, IEDM, 2006 2.
Y.H.Ha et al, An Edge Contact Type Cell for
Phase Change RAM Featuring Very Low Power
Consumption, Symposium on VLSI Technology Digest
of Technical Papers, 2003 3. Y.F.Lai et al,
Stacked Chalcogenide Layers Used as Multi-State
Storage Medium for Phase Change Memory, Appl.
Phys. A 84, 21-25, 2006
14
Phase-Change Memory

• I-V Characteristics

• Switch between two phases
• Crystalline phase (low resistance)
• Amorphous phase (high resistance)
• Programming
• Joule heating
• Reading
• Resistance of two states

1.Young-Tae Kim, Keun-Ho Lee, etc, Study on Cell
Characteristics of PRAM using the Phase-Change
Simulation Company, SISPAD, pp. 211-214, Sept.,
2001
15
Phase-Change Memory

• Structure

1.Young-Tae Kim, Keun-Ho Lee, etc, Study on Cell
Characteristics of PRAM using the Phase-Change
Simulation Company, SISPAD, pp. 211-214, Sept.,
2001
16
Phase-Change Memory

• RESET Pulse
• Crystalline to Amorphous
• High temperature and short duration
• SET pulse
• Amorphous to Crystalline
• Lower temperature for longer duration

17
Phase-Change Memory

• SET Programming
• modeled as a Continuous process following the
  Johnson-Mehl-Avrami (JMA) equation

Cx Crystalline fraction n Avrami
exponent t Time K Effective rate
constant K0 Constant Ea Activation
energy KB Boltzmanns constant T
Temperature (TgltTltTm)
18
Phase-Change Memory

• RESET depends on
• the magnitude of the current pulse
• the trailing edge of the current pulse
• the quenching time of the pc material

19
Phase-Change Memory

• Current Status

• SMIC will run its PCM process in its new fab. in
  SZ
• a 863 project is launched to support PCM research

20
Phase-Change Memory

• SPICE Macro-Model
• implemented in Verilog-A

Ron
Ix
Rcry
Ramo
Vth
Vx
21
Phase-Change Memory

• References

1 Dae-Hwang Kim, Florian Merget, Michael Forst,
and Heinrich Kurz, Three-dimensional simulation
model of switching dynamics in phase change
random access memory cells, Journal of Applied
Physics, 2007. 2 Ugo Russo, Daniele Ielmini,
Andrea Redaelli, and Andrea L. Lacaita, Modeling
of programming and read performance in
phase-change memories---Part I cell optimization
and scaling, IEEE Transactions on Electron
Devices, Vol.55, No.2, Feb. 2008. 3 F.
Pellizzer, A. Benvenuti, D. Ielmini, F.
Pellizzer, A. Pirovano, A. Benvenuti, and R. Bez,
Electrothermal and phase-change dynamics in
chalcogenide-based memories, IEDM Tech. Dig.,
2004. 4 Young-Tae Kim, et.al., Study on cell
Characteristics of PRAM using the Phase-Change
Simulation, Simulation of Semiconductor
Processes and Devices, 2003. 5 Young-Tae Kim,
et.al., Programming characteristics of phase
change random access memory using phase change
simulations, Japanese Journal of Applied
Physics, 2005. 6 GONG Yue-Feng, LING Yun, SONG
Zhitang, and FENG Songlin, Simulation of
phase-change access memory with ring-type
contactor for low reset current by finite element
modeling, Chinese Physics Letter, Vol.25, No.9,
2008. 7 A. Itri, D. Ielmini, A. L. Lacaita, A.
Pirovano, F. Pellizzer, and R. Bez, Analysis of
phase-transformation dynamics and estimation of
amorphous-chalcogenide fraction in phase-change
memories, Proc. IRPS, 2004. 8 D. Ielmini, A.
L. Lacaita, A. Pirovano, F. Pellizzer and R. Bez,
Analysis of phase distribution in phase-change
nonvolatile memories, IEEE Electron Device
Letters, 2004. 9 J. I. Lee, et.al., Highly
scalable phase change memory with CVD GeSbTe for
Sub 50nm Generation, Symposium on VLSI
Technology digest of Technical Papers, 2007. 10
Stefan Lai, Phase change memory a memory
technology for all applications, PPT. 11 R.
Bez, Chalcogenide PCM a memory technology for
next decade, IEEE IEDM, 2009. 12 A. Pirovano,
A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R.
Bez, Electronic switching in phase-change
memories, IEEE Trans. on Elect. Dev., 2004. 13
B. Schmithusen et.al., Phase-change memory using
an analytical phase space model, SISPAD,
2008. 14 Ugo Russo, Daniele Ielmini, Andrea
Redaelli, and Andrea L. Lacaita, Modeling of
programming and read performance in phase-change
memories---Part II program disturb and
mixed-scaling approach, IEEE Trans. on Elect.
Dev., Vol.55, No.2, Feb. 2008. 15 F. Pellizzer,
et.al., A 90nm phase change memory technology
for standalone non-volatile memory applications,
VLSI Symp. Tech. Dig., 2006.