STAR TOF Readout Electronics and DAQ

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STAR TOF Readout Electronics and DAQ

• Joachim Schambach
• University of Texas at Austin
• For the STAR TOF Collaboration

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The STAR TOF Collaboration

• Wenging Shen, Yugang Ma, Xiangzhou Cai
• Shanghai Institute of Nuclear Research (SINR),
• Shanghai, China
• Kejun Kang, Jianping Cheng, Yuanjing Li, Yulan
  Li, Yi Wang
• Tsinghua University, Beijing, China
• C. Whitten, H. Huang, G. Igo, V. Ghazikhanian,
• S. Trentalange, A. Tai, H. Long
• University of California - Los Angeles, Los
  Angeles, CA
• Hongfang Chen, Xin Dong, Xiaolian Wang, Ziping
  Zhang,
• Cheng Li, Lijuan Ruan, Shuwei Ye, Jian Wu, Ming
  Shao,
• Shengli Huang
• University of Science and Technology of China
  (USTC),
• Hefei, China
• G. Hoffmann, A. Ishihara, C.F. Moore, L. Ray, J.
  Schambach,

• P. Fachini, Zhangbu Xu
• Brookhaven National Laboratory
• Feng Liu, Lianshou Liu, Zhixu Liu, Jinghua Fu,
  Yuan Hu,
• Zhiming Li, Yuanfang Wu, Yan Lu
• HuaZhong Normal University, Wuhan, China
• Jin Li, Junguang Lu, Bingyun Zhang
• Institute of High Energy Physics (IHEP), Beijing,
  China
• Wenlong Zhan, Zhiyu Sun
• Institute of Modern Physics (IMP), LanZhou, China
• D. Hardtke, F. Retiere, N. Xu
• Lawrence Berkeley National Laboratory, Berkeley,
  CA
• L. Kotchenda
• Moscow Engineering Physics Institute, Moscow,
  Russia

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RHIC at BNL
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Multi-Gap Resistive Plate Chamber

• Developed in collaboration with the ALICE TOF
  group
• CERN experiment HARP has been using it for 2
  years
• Tested at CERN in 2000/01 and at AGS in 2002
• Prototype tray with 192 channels in current STAR
  run
• Timing-resolution lt 100ps, efficiency gt 95
• Measure large small scale correlations
• Increase statistics for multi-strange baryon
  measurements
• Extend the Pt range of IDd particles in STAR

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TOF Tray Design
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Electronics Overview
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On Detector Electronics
CERN HPTDC ASIC
Maxim 3760
AD96687
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Off Detector Interface Electronics
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DAQ Receiver
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TDIG TFEE Prototypes
TFEE
TDIG
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TDIG Prototype Jalapeno(SBIR with Lloyd
Bridges, Blue Sky Electronics)

• Microchip PIC18F8720 (with CANbus Serial port)
• Altera APEX 20K family PLD
• 2 HPTDCs, independent or chained
• JTAG interface
• Analog meant for comparison of slewing
  correction, section not (yet) implemented (final
  version will use time-over-threshold)

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Jalapeno Test Environment

• PLD used for I/O routing to/from TDC
• Micro used for power-up sequencing and interface
  to PC
• TDC programming via JTAG
• Current readout of TDC via JTAG as well
• JTAG software interface via Standard Test and
  Programming Language (STAPL), a JEDEC standard
  (JESD71), originally the JAM Programming Test
  Language from Altera
• Free STAPL player available from Altera,
  including source code
• Jam player code modified to write optional data
  files from JTAG output
• Jalapeno used to learn the (rather complicated)
  HPTDC ASIC
• Used to verify that proposed time resolution can
  be achieved
• Initially used pulsers, then interface with
  prototype TFEE

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HPTDC Architecture
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Internal Time Resolution

• HPTDC measures timestamps only
• Pulse generated by TDC clock is used to reset
  TDC, so all data points fall into approximately
  the same bin
• A delayed version of this pulse is used as hit
  (with delays generated by an HP8131A pulse
  generator)

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TFEE and TDIG Time Resolution

• Data from complete TFEE and TDIG chain
• Input pulser lightly coupled and capacitively
  loaded to simulate MRPCs