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LoranC Receiver

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Matt Anderson (ECE) Chris Birschbach (ECE) Christy Corner (EE) Matt Hayman (EE) Erin Mowbray (ECE) Background: What is Loran-C? ... – PowerPoint PPT presentation

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Title: LoranC Receiver


1
Loran-C Receiver
  • Team Deathstar
  • September 7, 2004

Capstone Fall 2004
2
Group Members
  • Matt Anderson (ECE)
  • Chris Birschbach (ECE)
  • Christy Corner (EE)
  • Matt Hayman (EE)
  • Erin Mowbray (ECE)

3
Background What is Loran-C?
  • Loran-C is a navigation system that was developed
    by the US Coast Guard.
  • The system is comprised of transmission stations
    located around the world.
  • The Loran-C signal is transmitted from these
    stations at specified intervals.
  • By measuring the time delay between transmissions
    a user can determine their position relative to
    the towers.

4
Loran-C Signal
5
Loran-C Signal continued
  • The Loran-C signal is transmitted on a 100kHz
    carrier.

6
Project Purpose
  • Our group will design a receiver that will be
    able to capture and decode the Loran-C signal
    maintained by the United States Coast Guard.
  • Our system will consist of three main parts the
    antenna/receiver, processing unit and personal
    computer.

7
Project Funding
  • Undergraduate Research Opportunities Program
    (UROP) Grant.
  • Amount 1750

8
Tentative Budget
9
Project Objectives
  • Capture a clean copy of the Loran-C signal
  • Determine Time Delays
  • Convert to a Latitudinal Longitudinal
    coordinates.

10
Outline of Approach
  • The system will consist of the following
    subsystems
  • Antenna Receiver
  • Analog-to-digital converter
  • Motorola 68K processor
  • Memory
  • FPGA
  • Serial Interface
  • PC
  • Power

11
Subsystems Diagram
Processing Unit
A/D Converter
Antenna/Receiver
FPGA
PC
Processor
RAM
12
Antenna Receiver Subsystem
  • The antenna/receiver will consist of a loop
    antenna with a active Butterworth filter to
    capture and amplify the fundamental signal
    received by the antenna.
  • This segment of the project serves the main
    purpose of capturing the Loran-C signal with
    minimal noise and preparing it for processing.

13
Analog-to-Digital Converter Subsystem
  • The A/D converter will sample the analog signal.
  • Sampling rate will be 1MHz.
  • The digital data will be sent to the FPGA .

14
FPGA Subsystem
  • The FPGA has a state machine for detecting the
    third zero crossing of the Loran-C signal.
    (Generates an interrupt)
  • It functions as a counter to measure the delay
    between pulses.
  • It includes an interrupt controller for the
    processor.

15
Processor Subsystem
  • Upon generation of an interrupt, the processor
    stores the counter data from the FPGA into RAM.
  • Performs operations on the counter data to
    determine time delays and stores the delays in
    RAM.
  • The microcontroller sends the time delay data to
    the serial interface with the PC.

16
RAM Subsystem
  • Holds the time delay and counter data for
    processing and transmission.

17
Serial Interface Subsystem
  • The communication interface between the PC and
    the processor.
  • Consists of a serial shift register RS-232
    logic level converter.

18
PC Subsystem
  • Displays the time delays.
  • Performs intensive conversion calculations to
    convert data into Latitudinal and Longitudinal
    coordinates.
  • Displays the Latitudinal and Longitudinal
    coordinates.

19
Power
  • Transform, rectify, and regulate voltage from
    standard 120V/60Hz outlet to required DC
    voltages. (Or purchase power supply)
  • Include portable power sources (battery or car
    adapter) if time permits

20
Tasks
  • Antenna Design
  • Filtering
  • PCB design
  • Memory interface
  • FPGA design
  • PC programming
  • PC interface
  • A/D interface
  • Processor programming
  • Power
  • Users Manual

21
Schedule
22
Division of Labor
  • Matt A
  • Power
  • Memory interface
  • Microprocessor Programming
  • Chris B
  • PC programming
  • Microprocessor programming
  • Users Manual
  • Christy C
  • Antenna/Filtering
  • Verilog Design
  • Users Manual
  • Matt H
  • Antenna/Filtering
  • PCB
  • Microprocessor Programming
  • PC programming
  • Erin M
  • Verilog Design

23
Risks and Backup
  • Receiving a clean copy of the signal
  • (Can generate a fake signal)
  • Baud rate generation for PC/processor
    communication
  • Buffer overflow (Sample slower)
  • Size and complexity of the state machine.
  • (Can shift tasks from the FPGA to the processor
    to compensate.)
  • RS-232 Communication on PC
  • (Manually entering data into the conversion
    program)

24
Above and Beyond
  • If time permits we shall include a LCD display on
    our receiver that displays the Loran-C time
    delays.
  • Portable power sources.
  • Cup Holders

25
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