SpaceCube IRAD Development Effort John Godfrey Code 561

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SpaceCube IRAD Development EffortJohn
GodfreyCode 561
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SpaceCube IRAD Overview
SpaceCube Architecture

• What is SpaceCube?
• SpaceCube is a Goddard IRAD effort to produce a
  generic, high density user-configurable
  subsystem. It is intended for applications which
  require a large amount of processing power and
  flexible interfaces with minimal mass, power, and
  cost.
• SpaceCube utilizes cutting edge reconfigurable
  FPGA technology, combined with a Rad-Hard by
  Architecture approach to allow for a large
  amount of logic in a small package.
• SpaceCube is capable of performing as a high
  speed network router, instrument CDH or
  communications adaptor.

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SpaceCube Architecture

• SpaceCube IRAD History
• The SpaceCube concept was originally developed
  for the Hubble Robotic Servicing and De-orbit
  Mission (HRSDM) to handle the need for high speed
  video processing, Pose estimation and routing to
  the space network.
• After HRSDMs cancellation, SpaceCube became an
  independent IRAD effort for approximately 8
  months before becoming a center-funded IRAD
  effort in Jan 2006.
• Currently, SpaceCube is baselined to perform a
  verification flight on HST SM 4 as the Relative
  Navigation System (RNS) CDH, Pose Processing
  unit and Bi-Static GPS Processor. Currently, RNS
  is scheduled for flight readiness in December,
  2007.

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SpaceCube IRAD Architecture
SpaceCube Architecture

• SpaceCube uses a stacked architecture composed of
  cards or slices connected via a connector
  running the length of the stack
• Slices can be made redundant and the stacking
  architecture allows any slice to communicate with
  any other slice thus allowing card level
  redundancy.
• Each slice has an individual enclosure which
  encloses it on 5 sides.
• Slices are stacked in whatever order desired and
  covered by a top plate.
• Up to two Power slices can be combined in a stack
  (one on the top, one on the bottom) to allow for
  a complete warm back-up system.

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SpaceCube IRAD Interfaces
SpaceCube Architecture

• Slice to Slice communications are handled via a
  combination of configurable high and low speed
  serial links.
• Redundant I2C Busses (100/400 Kb/S) provide for
  low speed command and telemetry functions
• High Speed busses such as Ethernet or SpaceWire
  provide for high speed communications (125Mb/s
  250 Mb/s per bus)
• Current implementation can handle up to 6 high
  speed busses and two low speed busses on the
  stack.
• I2C Communication is from hard microcontroller to
  hard microcontroller for critical functions.

• Slices can be configured with a variety of front
  panel options using either RS-422 or LVDS.
• SpaceCube can handle 8 full duplex Ethernet or
  SpaceWire links per processor slice.
• Removable front panels allow for differing
  connector configurations
• Default for Processor Slice is 2 51 pin MDM
  connectors.

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Space Cube IRAD Baseline Capabilities
SpaceCube Architecture

• SPECIFICATIONS
• CENTRAL PROCESSORS
• 4 x 450 MHz PowerPC 405, 32-bit RISC processors
• 2 x Xilinx XC4VFX60
• Redundant to handle SEFI
• 32K bytes of secondary (L2) on-die cache
• Common Processor Features are-
• 700 DMIPS RISC core
• 32-bit Harvard architecture
• 16 KB 2-way set-associative instruction and data
  caches
• Auxiliary Processor Unit (APU) controller
• 1.2V core voltage
• RECONFIGURABLE RESOURCES
• 2 x 56,880 logic cells
• 2 x 25,280 slices
• 2 x 4,176 Kb block RAM
• 232 18K block RAMs
• Example Helion AES core
• 447 slices, 10 block RAM, 2548Mbps performance

ETHERNET CAPACITY 8 x Ethernet Media Access
Controllers IEEE 802.3 compliant 10, 100, 1000
Mb/s Supports MII, GMII Does not use any system
gates. DIGITAL SIGNAL PROCESSING 128 XtremeDSP
Slices 18-bit by 18-bit, two's complement
multiplier with full precision 36-bit result,
sign extended to 48 bits. FLASH EPROM 256 Mbyte
of Flash EPROM application storage Flash has
separate power switching. Allows Flash to be
powered off when not in use. ROM 256 Mbyte of
ROM application storage backup for
Flash SOFTWARE SUPPORT Support for Linux,
VxWorks WindRiver MontaVista, BlueCat GNU GCC
Compiler
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Space Cube IRAD Baseline Capabilities
SpaceCube Architecture
SERIAL INTERFACES 32 x LVDS serial pairs Support
Ethernet, SpaceWire, or custom interface. 16550
compatible UARTs Aeroflex LVDS drivers and
Receivers RS422 can be substituted for LVDS if
desired STACKING CONNECTOR INTERFACE Airborne
Connector 72 pins Design uses no backplane or
motherboard. Low speed internal bus 400Kbps
Redundant I2C High speed bus TBD
Redundant Power Pins 3.3V, 5V RAD-HARD
SCRUBBER UT6325 RadHard Eclipse FPGA 320,000
usable system gates 24 dual-port RadHard SRAM
modules RadHard to 300K rad(Si)/sec OTHER
PERIPHERAL INTERFACES Available through stacking
connector by additional card slices Low Voltage
Power Converter card slice Same board size as
processor Provides low voltages from spacecraft
bus voltage Has 1553 interface, transformers and
signal drivers
ELECTRICAL SPECIFICATION 21V to 35V voltage input
through optional low voltage power converter card
slice Power Slice can provide 5V_at_ 2 Amps 3.3V_at_
6 Amps 2.5V_at_ 4 Amps all voltages are tolerant to
10 / -10 SAFETY SDRAM power is switched
separately to handle any potential latchup
conditions. ENVIRONMENTAL SPECIFICATION -20C to
55C (operating Baseplate temperature) -40C to
85C (storage baseplate temperature) 10 to 90
Relative Humidity, non-condensing (storage)
MECHANICAL SPECIFICATION 4 inches x 4 inches
(PCB) Box slice 4.25 inches x 4.25 inches x .75
inches/slice single board, double sided I/O
connectors 72 pin, Airborne Stacking 2 x 37 pin
LVDS
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SpaceCube IRAD Components
SpaceCube Architecture

• The Processor Slice is the brains of the stack
  and contains the four central processors (PowerPC
  405s) as well as a small RISC microcontroller to
  provide support and to mitigate single event
  effects in the PowerPCs.
• Processor slice contains the Cubes high speed
  external interfaces Upto 8 SpaceWire or
  Ethernet ports per slice.
• Each PowerPC is capable of providing up to 712
  Dhrystone MIPS and has access to approximately 3
  million reconfigurable gates.
• The Processor Slice can be combined with
  additional processor slices to provide additional
  computing power or for redundancy.

• The basic SpaceCube consists of a single
  SpaceCube Processor Slice (SCuP) and its Power
  converter (LVPC) Slice
• Power Slice forms the Base of the SpaceCube.
• Power Slice provides regulated low voltages from
  an unregulated 28V supply.
• Power Slice also provides support functions such
  as A/D Conversion for housekeeping, POR
  circuitry, and MIL-STD-1553B Communication.

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SpaceCube IRAD Processor Slice
SpaceCube Architecture

• SpaceCube processor slice is a miniaturized CDH
  system on a single 4 x 4 inch board
• Processing power is provided by 4 PowerPC 405
  processors which can be run either in parallel
  for speed or in a quad redundant voting scheme
  for SEU immunity
• Each PowerPC has its own independent SDRAM for
  program code/OS use.
• A soft-core SpaceRISC microcontroller is
  instantiated in the radiation hardened Aeroflex
  FPGA and acts as the monitor and controller for
  the PowerPCs and the Virtex logic.
• SpaceRISC is instruction set compatible with the
  PIC16F86 Microcontroller
• SpaceRISC is responsible for loading/re-loading
  the PowerPC code and scrubbing the Virtex
  configuration memory.
• SpaceRISC is also the I2C controller

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SpaceCube IRAD Processor Slice
SpaceCube Architecture

• SpaceCube Processor Slice provides configurable
  LVDS (or RS-422) I/O which can be used with IP
  Cores to implement a variety of interfaces such
  as SpaceWire, Ethernet, USB and CameraLink.
• Cores are available to perform most encoding
  functions Reed-Solomon, Convolutional, AES
  Decryption.

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Processor Performance
SpaceCube Architecture
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SpaceCube IRAD Processor Slice
SpaceCube Architecture
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Radiation Mitigation Redundancy
SpaceCube Architecture

• SpaceCube Processor Slice utilizes Xilinx Virtex
  devices to perform many of its core functions.
• These devices have a very high total dose
  tolerance, but are susceptible to SEUs.
• To eliminate the SEU effects, QMR (Quad Module
  Redundancy) is used.
• In a QMR scheme, the design is instantiated four
  times, twice in each Xilinx. These are voted
  together and if one output is different, it is
  discarded.
• User logic is scrubbed to prevent SEUs from
  corrupting instantiated designs.
• Processors are hard cores within the devices.
• SEU performance of processor cores Tested by GSFC
  in September 05.

• Each Virtex device is split into two functional
  units consisting of a processor and its
  peripherals
• Device level floor planning is used to ensure
  that two instantiations are physically separate
  to reduce the effects of multi-bit SEUs.

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Radiation Mitigation (Voting)
SpaceCube Architecture

• Two types of voting are implemented in SpaceCube
• Packet Based Voting is used for low volume, high
  reliability data generated by the PowerPCs. This
  data is sent to the SpaceRISC via serial port and
  voted on byte by byte by the SpaceRISC.
• Stream Based Voting is used for high volume data
  such as Ethernet or SpaceWire. Stream data is
  buffered using FIFOs within the Virtex, then sent
  to hard voters in the Aeroflex and voted bit by
  bit.
• Synchronization is handled by the Aeroflex.
• Errors detected and corrected by either voting
  scheme are reported to the SpaceRISC for
  inclusion in telemetry.

• For each output channel (e.g. MSM1, MSM2, Ku-band
  downlink, etc.) there are
• Four Parallel-Input-Serial-Output FIFOs (one per
  Xilinx PowerPC, located in Xilinx)
• One Control Line from Aeroflex to Xilinx(s) to
  initiate FIFO serial output
• One 4-input voter in Aeroflex
• SCuP board has four synchronous serial lines from
  Xilinx to Aeroflex (one per PowerPC)
• SCuP board has one synchronous serial line from
  Aeroflex to all four Xilinx PowerPCs.

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SpaceCube IRAD Power Slice
SpaceCube Architecture

• SpaceCube Power Slice provides regulated DC power
  to the assembled stack.
• Provides 5.0 V, 3.3 V, 2.5V, 1.8V
• 1.2V is locally regulated on Processor slice from
  the 1.8V supply
• Power Slice also provides MIL-STD-1553B
  transceivers and transformer.
• 1553 is controlled remotely from the Processor
  Slice.

• Power Slice provides A/D conversion capability to
  the stack for housekeeping using a 16 channel
  Trios ASIC.
• Provides voltage monitoring for all Power Slice
  generated voltages
• Provides internal temperature monitoring

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SpaceCube IRAD Power Slice
SpaceCube Architecture
1553 Transformer
5V DC-DC Converter
2.5V DC-DC Converter
3.3V DC-DC Converter
RS-422 Drivers
1.8V DC-DC Converter
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SpaceCube IRAD Current Status
SpaceCube Architecture

• SpaceCube Hardware tested and work has begun on
  SpaceCube software.
• 4 EDU PCBs were delivered to the SpaceCube team
  in Nov 05 All have been tested and are serving
  as platforms for software/VHDL development
• 1 Processor Slice delivered to ELC software team
  in early May 06.
• 1 Processor Slice / Power Slice delivered June
  22, 2006 to CCA Team.
• Voting Scheme Development is continuing, initial
  version is currently in testing.
• Flight Ethernet (D/S) port is currently in
  progress.
• RNS on SM 4 will be using SpaceCube and is
  currently scheduled for flight readiness in Dec
  2007.

Processor Slice Stacked on Power Slice

• Porting of Linux OS is currently in process
• Linux OS Training was held in June.
• cFE is being ported to Linux and will be ported
  to SpaceCube.