Session 10: The ISPD2005 Placement Contest

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Session 10The ISPD2005 Placement Contest
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Outline

• Benchmark Contest Introduction
• Individual placement presentation
• FastPlace, Capo, mPL, FengShui, APlace,
  NTUPlace, mFAR, KraftwerkDomino, Dragon2005
• Result Announcement
• Conclusion Future Work

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The ISPD2005 Placement Contest and Benchmark Suite
Gi-Joon Nam, Charles J. Alpert, Paul G.
Villarrubia, Bruce Winter and Mehmet Yildiz IBM
Corp.
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ISPD 2005 Placement Benchmark Suite
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ISPD 2005 Placement Benchmark Suite
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ISPD 2005 Placement Benchmark Suite
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ISPD 2005 Placement Benchmark Suite

• Real industrial ASIC designs
• Free space
• 54 - 85
• Affects wire-length significantly
• Macros
• Wider distribution of cell sizes
• I/Os perimeter and area array I/Os
• Various row configuration
• Clock logic included

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ISPD 2005 Placement Contest

• Open contest primarily for academic physical
  design community
• Covers majority of placement tools
• FastPlace, Capo, mPL, FengShui, APlace,
  NTUPlace, mFAR, KraftwerkDomino, Dragon2005
• Goals
• To provide new modern placement benchmarks
• To encourage to expose placement tools and
  results
• To provide an educational forum on the
  state-of-the-art placement algorithms

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Contest Format

• Each team is given 5 days to come up with the
  best results they can get
• Fixed window of time
• No limit on CPU resources
• Quality metrics
• Legality
• Half-perimeter bounding box wire length
• No timing metric
• No congestion metric

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Contest Timeline

• Jan. 12 Sample benchmarks released
• Mar. 20 Contest benchmarks posted
• Mar. 25 Solution submission due
• Apr. 6 Results announcement

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Outline

• Benchmark Contest Introduction
• Individual placement presentation
• FastPlace, Capo, mPL, FengShui, APlace,
  NTUPlace, mFAR, KraftwerkDomino, Dragon2005
• Result Announcement
• Conclusion Future Work

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Wire-Length Results
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Conclusions Future Works

• New placement benchmark suite ISPD2005
• ISPD2005 Placement Contest
• Better quality metrics for future contest
• Routability congestion

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adaptec2 Layout Figures
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adaptec2 Layout Figures
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adaptec2 Layout Figures