A BackEnd Design Flow for Single Chip Radios

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Yuen Hui Chee Winter Retreat 2003, Monterey
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Contributions

• Brian Otis
• Yuen-Hui Chee
• Richard Lu
• Ulrich Schuster
• Nathan Pletcher
• Susan Mellers
• Mika Kuulusa
• Mike Frank (Agilent)
• Dr. Bhusan Gupta (ST Microelectronics)
• Prof. Jan Rabaey
• Prof. Ali Niknejad
• DARPA

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Transceiver Goals
 

• Low power (lt100?W) to enable energy scavenging
• Low energy per bit ( 10nJ/bit)
• Short Range (lt 10m)
• Low data rate ( 10 kbps)
• Simple modulation scheme (on-off keying)
• Narrowband system (center frequency _at_ 1.9GHz)

 

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Major Milestones
FBAR-based low power oscillator
Test board transceiver
TX chain / RX test components
Prototype two-channel transceiver
Dec 01
Sep 02
Dec 02
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Test Board Transceiver
Brian Otis Richard Lu Susan Mellers Mika
Kuulusa Prof. Jan Rabaey
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Transceiver Architecture
RX Chain
TX Chain
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Test Board Design
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TX Chain
Center Frequency 1.91GHzOutput Power 700?W
(-1.5dBm) Transmitter Efficiency 9.5

• Low efficiency due to
• Matching network/low-power amplifier is not
  co-design for optimal efficiency
• Higher inductor losses than expected due to lower
  on-chip inductor Q

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RX Chain
Functional ReceiverPower consumed 2mW
Poor sensitivity due to insufficient RF gain
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Prototype Transceiver
Brian Otis Yuen-Hui Chee Richard Lu Nathan
Pletcher Prof. Jan Rabaey Prof. Ali Niknejad
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TX Chain

• Improved efficiency by
• Co-design the matching network with low-power
  amplifier for optimal efficiency.
• Ropt for PA and Ropt for matching network may not
  be the global Ropt.
• Use of low loss capacitive transformers
• Boosting the oscillator input drive and
• removing the pre-amplifier.

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Low-Power Amplifier
Yuen-Hui Chee
Spectrum of load (50?) current

• Center frequency 1.9 GHz
• Output Power 1.41mW (1.5 dBm)
• Efficiency 30

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RX Chain

• Improve sensitivity by
• Employing two gain stages in the front end
• 1st stage optimized for input power transfer and
  gain.
• 2nd stage optimized for frequency selection and
  gain.
• Using larger size devices in the envelope
  detector to reduce 1/f noise

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LNA
Richard Lu
No FBAR
RF out
Voltage gain 30 dB Power consumed 1.8
mW Noise Figure 2.6 dB Linearity (IIP3) -17.3
dBm
RF in
No source degeneration for higher gain
Input impedance matching
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RF Amplifier
FBAR
32 MHz Channel Spacing
Power consumed 600?W Voltage Gain 18
dB Bandwidth 3MHz
Brian Otis
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Envelope Detector
Transistors operate in sub-threshold Use of large
devices to reduce 1/f noise 98 settling time in
1.1?s Power consumed 360nW
Brian Otis
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Chip Layout
Standalone Low-Power Amplifier
Channel 1 TX Chain
Passive Test Structures
Standalone LNA
Two-channel Receiver
Standalone Differential Oscillator
Standalone Envelope Detector
Channel 2 TX Chain
Standalone RF Amplifier
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Looking ahead
B. Otis
Large output swings (0.85V pp) with 1V VDD
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Looking ahead
U. Schuster
Analog power scales sub-linearly with data rate
for the same BER Worthwhile to increase data rate
to reduce energy per bit Limited by ISI,
synchronization
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Thank You