Signal Integrity Interconnect Analysis

1
Signal Integrity Interconnect Analysis and
Design Constraints System Signal Planning made
Simple and Fun
2
Signal Integrity Planning and Analysis using
simulation tools
Agenda

• Overview High Speed Design Problems
• A Design Flow for Fast Interconnect Analysis
• Signal Integrity Constraints Definition
• Use of EDA tools for solving Signal Integrity
• Passing Constraints to your PCB Router
• Post Route Analysis of Net Topologies
• Why use simulation?

3
Why worry about High Speed Now?
Electronic Design is a Moving Target...

• Clock rates doubling every two years, 100MHz
  bus, 0.2u IC
• Board densities increasing with more vias,
  multi-layer etc.
• EMI compliance, adhere to FCC standards (EMC)
• High Density PCB routing (cross-talk)
• Mix-signal designs
• Study shows most designers either are facing
  problems now, or will
• encounter problems in the next 12 months.
• Building High Speed analysis expertise takes
  time

4
Define High Speed Problems?
Increasing clock speeds and packaging densities
can induce a set of problems that render a
logically correct design useless. Transmission
line Simulators can help find and prevent these
problems
Switching Errors - The primary causes of
switching errors are excessive interconnect
delays, an unstable signal
due to ringing, incorrect terminations, incorrect
net topology. Interconnect delays - Long trace
length reduce dielectric constant increase
signal to ground gap
increase signal speed reduce characteristic
impedance Ringing - Improperly terminated
lines excessive stubs mismatch interconnect
impedance Clock skew - Due to mismatch signal
lengths/delays, transmission line effects on
receivers Excessive Noise - Noise can
be induced by coupled lines in the form of
crosstalk, false switching
due to ringing and non-monotonic edges, or ground
bounce. Excessive DC loading - Improperly
terminated loads reduce number of loads,
incorrect net topology Device Malfunction -
Excessive overshoot and switching errors can lead
to device malfunction Mixed logic families -
Change components add terminator Fast Edge
Rates - Fast rise times can cause
transmission line effects on receivers
5
High Speed Designs Mandate Physical Constraints
Logical design meets physical
First Pass Success Requires The Following

• Logical design must drive physical
  implementation
• Net topology adjustments and driver/receiver
  selection
• Select optimum termination, based on trace
  length board geometry
• Specify correct Trace length, Width, impedance
  and delay
• Perform Transmission analysis to resolve Signal
  Integrity and termination issues
• EMI analysis to comply with FCC regulations

6
Constraints Development Process Flow

• Where can we apply transmission line simulation
  to synthesize constraints?
• Schematic level (Pre route)
• PCB Board level (After Placement)

What If Analysis -Net Topology -Termination -Board
Parameter
Interconnect Analysis Simulation
Form Factor Initial Placement
Final Place Route
Post Layout Verification
Physical Design - PCB Level
Logical Design - Schematic Level
EMI analysis Placement Constraints Routing
Constraints Signal Integrity-Post
Layout Cross-talk Analysis - Post
Layout Mechanical Constraints (height, keep out)
Interconnect Planning Termination Schemes Signal
Topology Analysis Timing Constraints Board
Parameters/Stackup Signal Integrity
Simulation Routing Strategies (daisy chain, star
burst etc.)
7
Constraints Synthesis Design Flow
HyperLynx LineSim
(.TLN)
OrCAD/Viewlogic/Mentor Schematic Editors
SI-Planner Studio
PADS PowerPCB Allegro BoardStation Accel-pCAD CadS
tar/Visula Veribest VB99a
PCB Board Layout CCT editor

• Bi-Directional data exchange
• Back annotation of Net and
• Component constraints
• Cross probe query data

PCB Netlist with HS BoardSim Rules
HIGH_SPEED_RULE MIN_LENGTH 1.60 MAX_LENGTH
2.00 STUB_LENGTH 0 MIN_DELAY 0.962589 MAX_DELAY
1.203236 MIN_CAPACITANCE 0.000000 MAX_CAPACITANCE
0.000000 MIN_IMPEDANCE 46.048080 MAX_IMPEDANCE
57.560100 "HyperLynx.Model" CMOS,3.3V,FAST "Val
ue" 16L8
PCB Vendor Specific Constraints Generated
After Net Optimization

• Read HyperLynx Simulation File
• (.TLN)
• Update Pin/Net Constraints

After back annotation of simulation data
8
PCBNavigator Design Flow
PCBNavigator provides the ability to enter design
constraints up front in the design process at the
schematic level, which reduces PCB delays.
MRP/ERP/CIS
PCB Layout PowerPCB PCAD/CADStar
PCB ECO File
OrCAD SWAP File
OrCAD, Innoveda Schematics
PCBNavigator
LIBS
PCB ASCII Netlist
OrCAD.dsn input ViewDraw .1 input
9
Introducing SI-Planner Studio
Signal Integrity Interconnect Analysis and Design
Constraints System

• Single integrated environment for planning
• optimizing interconnect High-Speed net
  topologies.
• Automatic net topology extraction and transfer
  into can
• LineSim with one click.
• Net topology viewer shows all net connectivity,
  drivers, receivers and termination points.
• User defined constraints
• Back annotation of simulation data into
  Schematic, and proper conversion into router
  constraints, as delay, track width, impedance,
  and length.
• Pass routing and placement constraints/rules to
  target PCB systems.

10
Interconnect Optimization
What If Analysis Design Space Exploration

• Select and analyze multiple termination schemes
  -
• Termination Wizard
• Series, Parallel, Thevenin, Diode etc.
• Evaluate which Drivers will provide optimum
  signal strength
• Generate multiple net topology scheme to
  minimize delay, and reflections.
• Daisy chain, starburst etc.

• Vary Board Properties and Stackup to achieve
  best results
• Review all Drivers/receives in the design
  quickly
• Quickly draw net topology in your schematic
  editor for analysis

11
Precience Family of HS-Products
PCBNavigator Suite

• Design Constraints Spreadsheet System
• ECO Manager for target PCB system
• BI-directional Schematic to PCB integration
• PCB Netlist generation with design rules

• PCB Layout back end Vendors
• PADS PowerPCB Rev-4.0/5.X
• Accel-pCAD Rev-2002-2003
• Zuken-Redac CADStar/Visula Rev All
• Cadence Allegro (All)
• Mentor Expedition Series All
• OrCAD LayoutPlus

SI-Planner Studio

• Design Constraints and Planning System
• Automatic net topology builder
• BI-directional Integration into LineSim
• Links to Schematic for net topology development
• Includes integrated LineSim Transmission line
  simulator
• Includes a license of PCBNavigator - Constraints
  Writer

12
Benefits ofUsing simulation tools similar
toSI-Planner Studio
Conclusion

• Reduce board turns, by providing correct
  simulation based PCB routing
• constraints for critical nets.
• Improve signal integrity, and signal quality up
  front in the design process
• Study signal drivers/receivers fan out
  conditions, early in the design process
• Provide correct termination schemes, based on
  transmission line
• analysis.
• Increase turn around time for high speed board
  designs.
• Save time over manual method of extracting net
  topology, and entering the data by
• hand in a transmission line simulator.
• Support IBIS model passing, from
  OrCAD/VIEWlogic component information
• systems (CIS) to Hyperlynx and PADS PowerPCB
  tools.

13
Using Constraints Manager to Pass PCB design
rules

• A design constraints and ECO management system
  for
• OrCAD/Innoveda/Mentor and Capture/ViewDraw
  users.
• Constraints Management
• PCBNavigator allows simple methods to enter
  specific PCB vendors design
• rules for NETS, COMPS, and PINS. Manage Design
  Rules in spreadsheets.
• Allows passing of PCB Component placement
  constraints into the
• target PCB system. Ex. Clusters, Height
  control, Rotation, Board side etc.
• Manage, and View design rules for
  Parts/Nets/pins through Design Explorer
• ECO Management
• Allows complete back annotation of ECO data
  from the PCB System
• into OrCAD Schematics
• Provides data synchronization between Schematic
  and Layout System
• Provides design debugging aids through OLE
  BI-directional cross-probing of
• NETS, and COMPS with a target PCB System