Optimal Design of DeltaSigma ADCs by Design Space Exploration

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Optimal Design of Delta-Sigma ADCs by Design
Space Exploration

• Ovidiu Bajdechi and Johan H. Huijsing
• June 12, 2002

Delft University of TechnologyThe Netherlands
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Outline

• ?? ADC design space
• Filter-level design
• Dynamic range evaluation
• Peak NTF database
• Architecture-level design
• Performance test
• Power and yield
• Experimental results
• Audio ADC
• xDSL ADC
• Conclusions

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?? ADC Filtering Characteristics
NTF max
ORDER
OSR
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?? ADC Topology Single Loop
BITS
(ai,bi, fi) coefficients map the NTF/STF on the
topology
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?? ADC Topology Cascaded
LOOPS2 BITS(N1, N2) ORDERS(2, 2)
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Filter-Level Exploration Algorithm
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Dynamic Range Estimation

• Ideally-shaped quantization noise

• Stable NTF-shaped quantization noise

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Quality of Estimate Single-Loop
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Quality of Estimate Cascaded
All solutions ORDER5
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NTF Magnitude Database
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NTF Magnitude Limits
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Architecture-Level Single-loop
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Architecture-Level Cascaded
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?? ADC Performance Requirements
DR flatness and average
SNDR OVL
SNDR slope and linearity
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Performance Test
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Power Consumption DT Circuits

• Differential switched-capacitor circuits

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Power Consumption CT Circuits

• Differential active-RC circuits

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Integrator Power Consumption
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Yield Analysis
Single-loop, 4th order, 1bit
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Audio ADC Solution Space
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Audio ADC Global Search
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Audio ADC Constrained Search
Only single-loop solutions
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xDSL ADC Solution Space
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xDSL ADC Global Search
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xDSL ADC Constrained Search
Only ORDER5, OSR16 solutions
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Conclusions

• An algorithm for exhaustive exploration of ?? ADC
  design space has been developed.
• Two-steps design improve overall exploration
  speed a fast filter-level design step and a
  slow, accurate architecture-level step.
• Final optimization and yield-analysis can be run
  on user-defined subsets of architecture-level
  solutions.
• Two state-of-the-art designs have been found
  among power-efficient solutions in design subsets
  for an audio and an xDSL ADC respectively.