Vector Potential Equivalent Circuit Based on PEEC Inversion

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Vector Potential Equivalent Circuit Based on
PEEC Inversion

• Hao Yu and Lei He
• Electrical Engineering Department, UCLA
• http//eda.ee.ucla.edu

Partially Sponsored by NSF Career Award (0093273)
, Analog Devices, Intel and LSI Logic
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Outline

• Introduction
• Vector Potential Equivalent Circuit Model
• VPEC Property and Sparsification
• Conclusions and Future Work

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Interconnect Model

• de facto PEEC model is expensive

• Accurate model needs detailed discretization of
  conductors
• Distributed RLC circuit has coupling inductance
  between any two segments

• Total 3,278,080 elements for 128b bus with 20
  segments per line
• 162M storage of SPICE netlist

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Challenge of Inductance Sparisification

• Partial inductance matrix L is not diagonal
  dominant
• Direct truncation results loss of passivity

• Existing passivity-guaranteed sparsification
  methods lack accuracy or theoretical
  justification
• Returned-loop ShepardTCAD00
• Shift-truncation (shell) KrauterICCAD95,
  Beattie TCAD01
• K-element DevganICCAD00, Ji DAC01
• Localized VPEC PacelliICCAD02

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K-Element Method

• Need to extend SPICE to simulate K-element Ji
  DAC01

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Contribution of Our Paper

• Derive inversion based VPEC model from first
  principles
• Replace inductances with effective resistances
• Develop closed-form formula for effective
  resistances
• Enable direct and faster simulation in SPICE

• Prove that circuit matrix in VPEC model is
  strictly diagonal dominant and hence passive
• Enable various passivity preserved sparsifications

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Outline

• Introduction
• Vector Potential Equivalent Circuit Model
• VPEC Property and Sparsification
• Conclusions and Future Work

• VPEC circuit model
• Inversion based VPEC
• Accuracy comparison

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Vector Potential Equations for Inductive Effect

• Vector potential for filament i

ith Filament

• Integral equation for inductive effect

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VPEC Circuit Model
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VPEC Circuit Model
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VPEC Circuit Model
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Recap of VPEC Circuit Model

• Inherit resistances and capacitances from PEEC

• Inductances are modeled by

• Effective resistances

• Controlled current/voltage sources

• Unit self-inductance

• Much fewer reactive elements

• leads to faster SPICE simulation

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Comparison with Localized VPEC

• Our solution

• Solution in localized VPEC PacelliICCAD02

(1) It is not accurate to consider only adjacent
filaments
(2) There is no efficient and closed-form formula
solution to calculate effective resistances
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Introduction of G-Element
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Closed-form Formula for Effective Resistance

• Major computing effort is inversion of
  inductance matrix
• LU/Cholesky factorization
• GMRES/GCR iteration (with volume decomposition)

Inversion Based VPEC
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Interconnect Analysis Based on VPEC

• Calculate PEEC elements via either formula or
  FastHenry/FastCap
• Invert L matrix
• 3. Generate full VPEC including effective
  resistances, current and voltage sources.
• 4. Sparsify full VPEC using numerical or
  geometrical truncations
• 5. Directly simulate in SPICE

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Spice Waveform Comparison
Full PEEC vs. full VPEC vs. localized VPEC

• Full VPEC is as accurate as Full PEEC
• Localized VPEC model is not accurate

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Spiral Inductor
Non-bus Structure Three-turn single layer
on-chip spiral inductor

• Full VPEC model is accurate and can be applied
  for general layout

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Outline

• Introduction
• Vector Potential Equivalent Circuit Model
• VPEC Property and Sparsification
• Conclusions and Future Work

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Property of VPEC Circuit Matrix

• Main Theorem
• The circuit matrix is strictly
  diagonal-dominant and positive-definite

Corollary The VPEC model is still passive
after truncation
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Numerical Sparsification
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Truncation Threshold
128-bit bus with one segment per line

• Supply voltage is 1V
• VPEC runtime includes the LU inversion
• Full VPEC model is as accurate as full PEEC model
  but yet faster
• Increased truncation ratio leads to reduced
  runtime and accuracy

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Waveforms Comparison

• Full VPEC is as accurate as full PEEC
• Sparsified VPEC has high accuracy for up to
  35.7 sparsification

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Geometry Based Sparsification - Windowed
For the geometry of aligned bus line
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Geometry Based Sparsification - Normalized

• Normalized VPEC
• normalized aligned coupling

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Geometrical Sparsification Results
32-bit bus with 8 segment per line

• Decreased window size leads to reduced runtime
  and accuracy
• Windowed VPEC has high accuracy for window size
  as small as (16,2)
• Normalized model is still efficient with bounded
  error

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Runtime Scaling

• Circuit one segment per line for buses
• The runtime grows much faster for full PEEC than
  for full VPEC
• full PEEC is 47x faster for 256-bit bus due to
  reduced number of reactive elements
• Sparsified VPEC reduces runtime by 1000x with
  bounded error for large scale interconnects

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Conclusions and Future Work

• Derived inversion based VPEC from first principle
• Shown that Full VPEC has the same accuracy as
  full PEEC but faster
• Proved that VPEC model remains passive after
  truncation

• To work on
• Fast iteration algorithms for inversion of L
• Model-order-reduction for VPEC