Path Based Buffer Insertion

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Path Based Buffer Insertion

• C. N. Sze, Charles Alpert, Jiang Hu, Weiping Shi
• Dept. of Electrical Engineering, Texas AM
  University
• IBM Corporation

2
Outline

• Introduction
• The problem
• How buffers are inserted for large circuits
• Algorithm details
• Buffer aware static timing analysis (STA)
• Definition of a path
• Off-path required arrival time (RAT) estimation
• Simultaneous buffer insertion and gate sizing
• Experimental results
• Conclusion

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Introduction

• Prediction from Intel Saxena et al. TCAD04
• The distance between buffers shrinks rapidly

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Introduction (2)
Saxena, et al. TCAD 2004

• Buffer insertion and sizing is one of the most
  effective method for reducing interconnect delay

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Previous Works

• Net based buffer insertion
• van Ginneken dynamic programming algorithm
  framework (VGDP) ISCAS 90
• Delay minimization based on Elmore delay
• Minimize power (buffer cost) with timing
  constraint and consider buffer library ICCAD 95
• Noise avoidance DAC 98
• Higher-order delay model DAC 99
• On-chip inductance DAC 99
• VERY FLEXIBLE!!
• (blockages, invertors/polarity )

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How Buffers are Inserted?

• Buffer Insertion for large circuits
• Minimize buffer area/power subject to timing
  constraint
• Apply net based buffer insertion
• Pick a net n1 along critical path
• Insert buffers on n1
• Pick another net n2 and continue
• Repeat until timing constraint is satisfied

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Whats Wrong with Net Based?
net A
net B
S1
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Possible Solutions

• Network Based Buffer Insertion
• (Liu,Aziz,Wong,Zhou ICCD99,DATE00)
• Based on Lagrangian relaxation and local
  refinement
• Assume that buffers are inserted at all branches
• The runtime of the algorithms scale badly
• Path Based Buffer Insertion (PBBI)
• Directly apply VGDP algorithm
• Can be extended to handle complicated practical
  problems (e.g. accurate delay model, noise )
• Runtime scales much better

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Comparison

• CPU runtime

network based
PBBI
net based
Buffer resource efficiency
PBBI
network based
net based

• - assumptions
• difficult to handle
• practical problems

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Overview of PBBI

• Buffer aware critical path analysis (STA engine)
• From a path to a tree
• Off-Path RAT estimation
• Distinct paths

tree1
Critical path1
Critical path2
tree2
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Finding Critical Paths

• Traditional static timing analysis is inadequate
• Buffering significantly affects delay on
  interconnect
• Buffer blockages
• Neglecting buffers may cause inaccurate
  estimation of critical paths
• In our implementation
• Linear time delay estimation of buffered
  interconnect ICCAD04

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Buffer Insertion For a Path

• Merged trees
• Gate special buffer candidate must added /
  fixed size
• Bigger trees
• Buffer insertion speedup techniques ASPDAC 05

special buffer candidate
tree1b
tree1c
tree1a
Critical path1
tree1d
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Off-Path RAT Estimation

• Input of VGDP algorithm
• RAT at sinks
• Buffer solution can affect RAT estimation

Critical path1
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Off-Path RAT Estimation (2)

• Slack distributed along the path

z
a
i
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PBBI and Gate Sizing

• Integrating gate sizing into path based buffer
  insertion is straight-forward
• Sizing up a gate
• Decrease downstream interconnect delay
• Increase upstream interconnect delay
• Gate sizing at sinks gives more control
• Example

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PBBI and Gate Sizing (2)

• Gate sizing at sinks
• Adjust RAT in order to compensate the increase in
  downstream delay

Wire capacitance of one optimal buffer interval
Output resistance of original gate
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Experiment Setting

• 12 combinational circuits
• Randomly generated from IBM real nets
• Buffer blockages from real layout
• 4 types of buffers (inverted/non-inverted)
• Buffer insertion considers both slew/cap
  violations and timing

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Experimental Results

• Timing constraints
• Find min-delay buffer insertion solution
• Set RAT such that worst-slack 0
• PBBI uses 15 less buffer resource than net
  based

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Experimental Results (2)

• PBBI uses 5x more CPU time
• CPU time is on general empirically linear to
  the size of the circuit and the buffer candidate
  locations
• Buffering for the largest circuit in 40 sec

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Results - with Buffer Blockages

• Same timing constraints setting
• PBBI uses 29 less buffer resource than net
  based
• CPU time usage is similar

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Results PBBI Gate Sizing

• Same setting for timing constraints
• PBBIGS uses 71 less area than net based
• Total CPU time for PBBIGS is 7 minutes
• Path based buffer insertion works very well with
  gate sizing

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Conclusion

• Increasingly more buffers in circuit designs
• Buffer insertion in a more elaborated manner
• Propose a path based buffer insertion approach
• Obtain a better buffer usage efficiency due to
  its global view
• Our approach is more practical in terms of CPU
  runtime and flexibility when comparing to network
  based methods
• Reduce buffer area by 29
• Includes all buffer counts
• With buffer blockages on the layout
• Reduce buffer/gate cost by 71 on average

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Thank you

• Questions?