An Energy Saving Strategy Based on Adaptive Loop Parallelization

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An Energy Saving Strategy Based on Adaptive Loop
Parallelization

• I. Kadayif and M. Kandemir
• Pennsylvania State University
• University Park, PA 16802
• M. Karakoy
• Imperial College
• London SW7 2BZ, UK

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Objective

• To evaluate an adaptive loop parallelization
  strategy and measure the potential energy savings
  when unused processors and their caches are shut
  down

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Outline

• Multi-Processor-on-a Chip (MPoC)
• Our MPoC Architecture
• Energy Model
• Adaptive Loop Parallelization
• Experimental Results
• Conclusion and Future Work

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MPoC

• Each processors can operate independently
• On-chip-memory (SRAM)
• Synchronization logic
• Processors share data
• I/O and interconnect
• Array-intensive loop dominated applications can
  take advantage of MPoC
• Source level loop parallelization

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VLIW/Superscalar Processors

• May provide a certain level of ILP
• Not scalable to provide high level of performance
  (e.g., for wireless environments)
• Power consumption does not scale linearly (due to
  complexity of instruction dispatch, issue units,
  etc.)

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MPoC Examples

• Suns MAJC-5200
• General purpose multi processor systemon a chip
  with 2 processors
• Multimedia computing and networking applications
• IBM Power4
• More processors on the same chip

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Our MPoC Architecture

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Our MPoC Architecture Cont.

• Simple pipelined architecture oneinstruction
  issue per cycle
• Simple, identical processors
• Data cache and instruction cache
• Low design and verification costs
• A large, off-chip memory (DRAM)
• A simple synchronization mechanism

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Synchronization Mechanism
8 bit register

CPU0
CPU7
CPU1
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Objective

• To save leakage energy by shutting off unused
  processors and their caches

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Important Parameters

• Energy reduction factor (ERF)
• Re-synchronization penalty (RP)

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Energy Model

• Components
• Data path, clock circuitry, caches andoff-chip
  memory
• SimplePower tool for data path clock circuitry
• 0.35 micron technology
• Analytical cache energy model byShiue et. al.
• 4.95nJ off-chip energy consumptionper access
• Omitted control circuitry

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Shutting Off Unused Processors

• Only a small subset of processors may generate
  best execution time
• Intrinsic data dependences
• Overhead of creating a large number of threads
• Shutting off unused processors tosave energy

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Profiling
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Profiling Cont.

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Adaptive Loop Parallelization

• Determining the number of processorsto execute
  each loop nest
• Dynamic
• Static
• Our approach is static, activation/deactivationat
  runtime
• Policy
• The criterion to determine the numberof
  processors
• Execution time based

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Processor Activation
idle
idle
idle
re-synch
re-synch
active
active
active
v1
v3
v2
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Normalized Energy Consumption (V2)
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Performance Penalty (v2)
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Normalized Energy Consumption (v3)
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Conclusion and Future Work

• First step for evaluating adaptive
  parallelization from energy perspective
• Model more accurate communication between
  processors
• Speculative execution
• Modeling energy consumption of other components

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For More Information

• www.cse.psu.edu/mdl
• mdl_at_cse.psu.edu