OnChip Logic Minimization

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On-Chip Logic Minimization

• Roman Lysecky Frank Vahid
• Department of Computer Science and Engineering
• University of California, Riverside
• Also with the Center for Embedded Computer
  Systems, UC Irvine
• This work was supported in part by the National
  Science Foundation, the Semiconductor Research
  Corporation, and a Department of Education GAANN
  fellowship

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Introduction

• Boolean logic minimization typically used during
  logic synthesis
• Two-level logic minimization can be considered as
  a general optimization technique
• Many applications can benefit from using logic
  minimization dynamically
• IP routing table reduction
• Access control list (ACL) reduction

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On-Chip Minimization Applications (IP Routing
Table Reduction)
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On-Chip Minimization Applications (IP Routing
Table Reduction)

• Longest Prefix Match
• Ternary CAM (McAuley Francis, 1993)
• Store 0,1,
• Store IP address as TCAM entry
• Store prefix length using the TCAM entries mask
• Fast
• Smaller hardware resources than binary CAM
• Very large power consumption
• How can we reduce hardware resources and power
  consumption?

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On-Chip Minimization Applications (IP Routing
Table Reduction)

• Mask Extension (Liu, 2002)
• Uses two-level logic minimization
• Performing minimization for each update too slow
• Incremental update
• Existing minimized set becomes dont care set
• New route becomes single entry in on set
• Achieves an average of 50 updates/second
• Not considering communication, though

Original TCAM Entries
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On-Chip Minimization Applications (Access
Control List Reduction)

• Access Control List (ACL)
• Used to restrict IP traffic through network
  routers
• ACL size can range anywhere from from 300 (UCR
  CSE Dept.) to 10,000 (AOL)
• Common use is to block a particular protocol or
  port number to avoid attacks such as Denial of
  Service attacks
• ACL Minimization
• Similar approach as used for IP routing table
  reduction
• However, order of the list must be preserved

ACL Input Format
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Introduction(Off-chip Logic Minimization)

• Slow due to communication
• Sensitive to server failures
• Security issues

Router
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Introduction(On-chip Logic Minimization)
Router
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On-Chip Logic MinimizationRequirements

• On-chip Logic Minimization Requirements
• Data Memory Resources
• On-chip minimization algorithms must be very
  memory conscious
• Instruction Memory Resources
• On-chip minimization algorithm must incorporate
  simplified approaches that result in acceptable
  designs
• Execution time
• Limited data and instruction memory will likely
  lead to longer execution times
• Must still remain reasonable
• Quality of results
• Must be capable of producing solution relatively
  close to optimal

Focus on developing an on-chip logic minimization
tool that produces acceptable results with
reasonable increases in execution time while
using limited memory resources.
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ROCM

• ROCM Riverside On-Chip Minimizer
• Two-level minimization tool
• Utilized a combination of approaches from
  Espresso-II (Brayton, et al. 1984) and Presto
  (Svoboda White, 1979)

IterativeExpand(F,D,c) W c' c for
i1 to c c' Expand(c',i) (val,W')
ValidExpansion(F,D,c') if val true
W W ? W' else Revert(c',i)  
return (c',W)
Optimize(F,D) OrderCubes(F) for i1 to
F c Fi (c',W)
IterativeExpand(F,D,c) F (F ? c') - W

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ROCM Results Quality (Full Routing Table
Reduction)
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ROCM Results Performance (Incremental Update
Execution Time)
On a 500 MHz Sun Ultra60
On a 40 MHz ARM 7
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ROCM Results Memory (Code Size and Data Memory
Usage)
Data Memory Usage
Code Size
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ROCM Results Quality(Access Control List
Reduction)
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Customizing ROCM

• ROCM Customization
• Beneficial to optimize an algorithm for a
  particular application
• Customize ROCMs data structures and algorithms
  for a particular input size
• Require less memory
• Reduce dynamic memory allocation
• Improve performance
• Created ROCM-32 customized for IP routing table
  reduction

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Customized ROCM-32 Results(IP Routing Table
Reduction)
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Conclusions

• Presented Riverside On-Chip Minimizer (ROCM)
• Feasible to execute logic minimization on chip
• Can be executed on an embedded 40 MHz ARM7 in
  seconds for real networking problem sizes
• Requires small code size (22 kilobytes)
• Requires small data memory (1 megabyte)
• Produces good results
• On average only 2 larger than exact minimization
• Shown usefulness for networking applications

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Future Work

• More Applications
• May appear now that on-chip minimization is
  feasible
• Dynamic HW/SW Partitioning
• Dynamically partition executing binary to on-chip
  configurable logic
• Logic minimization is used during the logic
  synthesis stage
• Initial work on dynamic HW/SW partitioning
  presented at DAC 2003 yesterday in session 15