Variation Resilient LowPower Circuit Design Methodology using OnChip Phase Locked Loop

1
Variation Resilient Low-Power Circuit Design
Methodology usingOn-Chip Phase Locked Loop
Kunhyuk Kang, Keejong Kim, and Kaushik
Roy Electrical and Computer Engineering Purdue
University
2
Motivation Circuit Manufacturability
inNano-Scale Technology

• Process Variation Reliability Degradation leads
  to degraded manufacturability of nano-scale
  circuits ? Reduced design margin power, area,
  design effort

3
Outline

• Previous Works
• Basic concept of PLL
• Charge-Pump PLL (CPPLL)
• Sensor circuit using PLL
• Process corner sensing
• Temperature and reliability sensing
• Corrective actions using sensor circuit
• Variation Resilient ABB System (VR-ABB)
• Nominal design approach
• Conclusion

4
Previous Works Adaptive Techniques
RAZOR Technique
Self-Repairing SRAM

• Dynamic Keeper Sizing C. H. Kim, VLSI Circuit
  Symposium03
• Critical Path Isolation, Two-Cycle Operation S.
  Ghosh, ICCAD06
• Razor Technique D. Ernst, MICRO03
• Self-Repairing SRAM S. Mukhopadhyay, VLSI
  Circuit Symposium06
• Adaptive Body Biasing J. Tshanz, ISSCC02

5
Concept of Phase Locked Loop (PLL)
VCO
inp
outn
Delay Cell
inn
outp
inn
Vcnt
LPF
UP
PFD
CP
VCO
DOWN
1/N
Vcnt

• Essential design block in modern microprocessor
• Source of stable on-chip clock generation
• Designed to sustain PVT resilient clock signal

6
PLL Operation under Variations
VCNT
VCNT
VCNT

• VCNT is a signature of on-chip PVT skew

7
Overall Framework
Potential Failure
On-Chip Resources
PLL Vcnt signal

• On-Chip PLL

Hazard Sources
On-Chip PVT Skew

• Process var. (Inter-die)
• Environmental var. (Temp., VDD)
• Reliability degrad. (NBTI, HCI)

Dynamic Techniques
Corrective Actions

• DFS, DVS
• ABB

PVT-Robust Stable Design
Avoid Circuit Failures
8
Process Variation Sensing with PLL
3.5
Required Vcnt for 2.2GHz clock

• Inter-die process corners can be determined
• Random sources of variations cancels (RDF)
• Initial Power-ON detection

FF
3
TT
2.5
SS
CLKVCO (GHz)
2
1.5
1
0.5
0.6
0.7
0.8
Vcnt (V)
9
Temperature NBTI Sensing with PLL
0
.
68
PLL
_at_
NORM
c
c
c
PLL_at_NORM
25
75
125
0
.
70
0
.
66
13.6 increase in 3 years due to NBTI

)
0
.
39
mV
/
C
V
(
Vcnt (V)
t
n
c
V
0
.
62
0
.
62
9
11
.

increase in V
cnt

120
with
C increase
0
.
6
0
.
58
4
5
6
7
8
9
10
10
10
10
10
10
Time
(
s
)
3 years
0
.
58
20
40
60
80
100
120
140

Temperature
(
C
)

• Capable of sensing environmental and temporal
  variations
• Dynamic sensing immediately unlock PLL when
  there is potential failure

10
Applying Corrective Actions
Possible Failure
FBB applied
SLOW Corner die
ALU1
ALU2
ALU1
ALU2
FPU
FPU
PLL (SLOW) Vcnt ?
PLL
Register
Register
Basic assumption PLL Vcnt signal and process
skew in other circuit blocks are correlated
performance variation
11
Correlation between PLL and other Logic Circuits
2000 M.C _at_25C ? 0.82
22
125C STRESS _at_NORM
INTERMAX
21
109
20
INTRAMAX _at_Vcnt0.6
19
245ps
60ps
108
107
increase in DRCA
INTRAMIN
18
105
106
17
104
INTERMIN
16
15
10
11
12
13
14
15
16
increase in Vcnt
ltUnder Process Variationgt
ltUnder NBTI Degradationgt

• Process Skew at Ripple Carry Adder (RCA)
  monitored
• High correlation between PLL and other logic
  circuit on the die were also observed

12
Variation Resilient Adaptive Body Biasing
(VR-ABB) System
pbody
PLL
CLKREF
pbodyBBG
0 1
8 bit RCA
PFD
pll_lock
Blt07gt
Slt07gt
Body Bias Generator
pbody
Alt07gt
A0
B0
A1
B1
A7
B7
other circuit blocks
CP/LPF
cin
cout
F/A
F/A
Vcnt
nbody
S0
S1
S7
VCO
8 FAs
nbody
nbodyBBG
pll_lock
pll_lock
0 1
pll_lock
CLKVCO
clock buffers

• VR-ABB system enables nominal design of a system
• 8 bit Ripple Carry Adder (RCA) employed
• CMOS 130nm technology node

13
VR-ABB Transient Simulation
PLL re-locking and computing new BB
Applying ABB to the RCA block
Optimal BB computed
setup margin -10ps
New locking condition calibrated
pbody
FBBp 1.0V
setup margin 10ps
cin
clk
PLL unlocked due to NBTI
Vcnt 0.68V
cout (FBB)
Vcnt 0.6V
FBBn 0.2V
cout (ZBB)
pll_lock
FBB applied
nbody
Time (ns)
0.2
0.441
Time (ns)
PLL locking 60us
1.07
1.12
0.1

• Transient simulation applied
• Potential scenario PLL unlocking at 0.2ns due to
  NBTI
• ABB computed to avoid negative setup margin in RCA

14
VR-ABB System Design Layout
CPPLL
6 bit BBG
500 um
8 bit RCA

• CMOS 130nm Technology, under fabrication
• 1.2V VDD, 1.6nm TOX

15
Nominal Design Approach
Design Target D0
of chips
2) P.V NBTI
1) P.V
circuit delay

• Design space reduces with process variation (D1)
  and NBTI degradation (D2)
• Nominal design constraint (D0) can be applied
  when using VR-ABB

16
Reduction in Design Space

• Design under process variation and NBTI
  degradation using conventional method and VR-ABB
• Significant power and area reduction using VR-ABB
  approach

17
Conclusion

• PLL provides a low-cost and high-gain sensing
  capability of PVT variations
• High correlation exists between PLL Vcnt and PVT
  skews in other logic blocks
• ABB applied based on the Vcnt to avoid possible
  circuit failures
• VR-ABB system enables nominal design enabling
  low-power and reduced area