Factors Affecting Operating Speed

1
Factors Affecting Operating Speed

• Charging and discharging of load capacitances
• Use of totem-pole
• Storage time delay (getting the transistor out of
  saturation)
• Use of Schottky Transistor

2
Schottky TTL Diode

• Metal to n-type semiconductor diodes.
• Involves only the flow of majority carriers.

Anode (metal)
Cathode n-type semiconductor
3
Schottky TTL

• A schottky diode placed between the base and
  collector of an npn BJT results in a schottky
  transistor.

Circuit Configuration
Schottky Transistor symbo l
4
Types of Schottky TTL

• (LS)TTL Low Power Schottky TTL
• (AS)TTL Advanced Schottky TTL
• (ALS)TTL Advanced Low Power Schottky TTL

5
Summary (session 2)

• TTL Logic Family
• Basic TTL NAND Gate
• Wired Logic
• Standard TTL
• Open Collector (to decrease power dissipation)
• Totem-pole (to increase switching speed)
• Wired Totem-pole (not possible)

6
Summary (session 2)

• Variations in TTL
• Three State TTL (with enable input)
• Schottky TTL (to decrease storage time delay)

7
Session 3

• Introduction to MOSFET
• (Basic structure,states,formation of an
  n-channel)
• N -Channel Enhancement Type MOSFET
• N-channel Depletion Type MOSFET
• P-channel MOSFETs
• MOSFET As a Register

8
Session 3 contd

• NMOS And PMOS Logic Gates
• CMOS Logic Gates
• NOT gate
• NOR gate
• NAND gate

9
FET

• FET is a Field Effect Transistor.
• Only one type of charge carrier flows through the
  semiconductor material.
• They are also called Unipolar Transistors.

10
Types of FET

• JFET Junction field effect transistor
• commonly used for linear or analog circuits.
• MOSFET Metal Oxide Semiconductor
  Field Effect transistor
• Commonly used for logic circuit design.

11
MOSFET Properties

• Advantages
• compact and simple to fabricate
• Can be used to realise a resistor(high values)
• Low power dissipation
• Disadvantage
• slower in switching compared to TTL.

12
Basic MOSFET Construction
13
Basic Structure
N-channel Enhancement Type
Metal
Oxide layer (SiO2)
14
Important MOSFET Parameters

• Maximum Drain-Source Voltage ( VDS)
• VDS is the maximum instantaneous operating
  voltage.
• Continuous Drain Current (ID)
• ID is the maximum current the MOSFET can carry
  sometimes specified at a particular junction
  temperature.
• Maximum Gate-Source Voltage VGS
• VGS is the maximum voltage that can be applied
  between gate and source without damaging the gate
  insulation.
• Gate Threshold Voltage, VT
• VT is the minimum gate voltage at which the
  transistor will turn ON 

15
OFF State of MOSFET

• Source-Substrate pn junction is zero biased.
• Drain-Substrate pn junction is reverse biased.
• No current flows between source and drain.
• Transistor is said to be OFF

16
Formation Of N-channel

• As VGS is increased, electric field is created
  between S and G. Electrons are attracted towards
  the ve gate terminal.
• When VGSVT, a channel is formed, ID flows and
  transistor is ON .

17
ID-VDS Characteristics with VGS constant

• With VGSconst the graph for different values of
  VDS (large values) is as given in figure.

18
N-channel Before Pinch Off

• Keeping VGS const and increasing VDS has the
  effect that the channel width starts decreasing
  at the drain.

19
N-channel At Pinch Off

• The process continues till the channel width
  becomes zero at the drain . This condition is
  called pinch -off

20
N-channel After Pinch Off

• After pinch off ID is not significantly
  dependent upon VDS.

21
N-channel Depletion Type MOSFET

• A lightly doped n-channel is placed between two
  heavily doped n-regions(n).
• When VGS 0 , the transistor is ON

Lightly doped n-channel
22
Formation Of N-channel

• When VGS is ve the channel depletes.
• At some VGSgt - VT drain and source terminals are
  disconnected and transistor is OFF.

23
MOSFET Symbols
a)n-channel enhancement type b)p-channel
enhancement type c)n-channel depletion type
d)p-channel depletion type
24
Enhancement Type MOSFET as Register

• Gate and Drain terminals are connected.
• VDSVGS

25
P-Channel Depletion Type MOSFET as Register

• Channel already exists at VGS0
• Gate is connected to Source.

Resistance is directly proportional to channel
length and inversely proportional to channel
width.
26
NMOS NOT Gate

• Q2 acts as load register.
• Q2 is always on.
• Resistance of Q2(on)gtQ1(on)

27
NMOS NOR Gate
28
NMOS NAND Gate
29
PMOS NOT Gate

• A negative voltage at gate terminal (enhancement
  type p-channel)is needed to form a channel.
• Positive logic
• Logic 0 -Vddlt-Vt
• Logic 1 0V (gnd)

30
PMOS NOR Gate
31
PMOS NAND Gate
32
CMOS NOT Gate
33
2 Input CMOS NOR Gate
34
2 Input CMOS NAND Gate
35
Summary

• MOSFETs
• N-channel Enhancement Type
• N-channel Depletion type
• Logic Gates With MOSFETs
• PMOS, NMOS, CMOS Networks
• NOT, NOR, NAND Logic

36
MOSFET Fan-Out Effect ON Speed