CHAPTER 2 FET AMPLIFIERS

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CHAPTER 2FET AMPLIFIERS
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FET AMPLIFICATION
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FET AMPLIFICATION

• Transconductance, gm
• is the change in drain current (?ID) for a given
  in gate-to-source voltage (?VGS) with the
  drain-to-source voltage constant.
• Expressed as a ratio
• unit of siemens (S)

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• Equivalent circuit
• rgs is assumed to be infinitely larger
• Open circuit between gate and source
• rds is assumed large enough to neglect

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• Voltage gain
• Ac voltage gain
• Where
• Therefore

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Example 1

• A certain JFET has a gm4mS. With an external
  as drain resistance of 1.5 k?, what is the ideal
  voltage gain?
• Solution
• Av gmRd
• (4mS)(1.5k?)
• 6

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• Effect of rds on gain
• if rds is not sufficiently greater than Rd (at
  least 10 times greater), the gain is reduced to
  this equation.

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Example 2

• The JFET in example 1 has an rds10k?.
  Determine the voltage gain when rds is taken
  into account.
• Solution
• The voltage gain is reduced from a value of 6 in
  example 1 because rds is in parallel with Rd.

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Effect of External Source Resistance on Gain
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Example 3

• A FET equivalent circuit is
• shown in figure. Determine the
• voltage gain when the output
• is taken across Rd. Neglect rds.
• Solution
• Rs reduces the voltage gain from 6 in example 1
  to 1.85

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COMMON-SOURCE AMPLIFIERS
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COMMON-SOURCE AMPLIFIERS

• A common-source amplifier is one with no source
  resistor
• The source is connected to ground
• Also known as self-biased configuration
• A self-biased common-source n-channel JFET
  amplifier with an ac source capacitively couple
  to the gate
• This configuration requires only one dc supply
• to establish the desired operating point
• The resistor RG serves two purposes
• It keep the gate at approximately 0Vdc (because
  IGSS is extremely small)
• Its large value prevents loading of the ac signal
  source

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Figure 1 JFET common-source amplifier
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• The bias voltage is produces by the drop across
  RS
• The bypass capacitor C2 keeps the source of the
  FET effectively at ac ground
• The input signal voltage causes the
  gate-to-source voltage swing above and below its
  Q-point value (VGSQ)
• Causing a corresponding swing in drain current
• As a drain current increased, the voltage drop
  across RD also increased
• Causing the drain voltage to decrease
• The drain current swings above and below its
  Q-point value in phase with the gate-to-source
  voltage
• The drain-to-source voltage swings above and
  below its Q-point value (VDSQ) and it 180 out of
  phase with the gate-to-source voltage (figure 1b)

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A graphical picture

• Figure 2a described for an n-channel JFET is
  illustrated graphically on the transfer
  characteristic curve
• It shows how a sinusoidal variation, Vgs produce
  a corresponding sinusoidal variation in Id
• As Vgs swings from its Q-point value to a more
  negative value, Id decreases from its Q-point
  value
• As Vgs swings to a less negative value, Id
  increases

Figure 2
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A graphical picture

• Figure (b) described for an n-channel JFET is
  illustrated graphically on the drain
  characteristic curve
• Signal at the gate drives the drain current
  equally above and below the Q-point on the load
  line (as indicated by the arrows)

Figure 2
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DC Analysis

• Step
• Determine the dc bias value
• Develop a dc equivalent circuit by replacing all
  capacitors with opens
• Determine the ID
• If the circuit is biased at the midpoint of the
  load line
• Otherwise,

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Figure 3
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AC Equivalent Circuit

• Step
• Replace the capacitors by effectives shorts
  (based on the simplifying assumption that Xc0 ay
  the signal frequency)
• Replace the dc source by a ground (based on the
  assumption that the voltage source has a zero
  internal resistance)
• The VDD terminal is at a zero-volt ac potential
  and therefore acts as an ac ground (figure 4a)

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Figure 4 AC equivalent for the amplifier
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Signal Voltage at the Gate

• An ac voltage source is shown connected to the
  input in figure 4b
• Since the input resistance to a FET is extremely
  high
• All input voltage from the signal source appears
  at the gate with very little voltage dropped
  across the internal source resistance.

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Voltage Gain

• The expression for FET voltage gain that applies
  to the common-source amplifier is
• The output signal voltage Vds at the drain is
• or
• where

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Example 4

• What is the total output of the unloaded
  amplifier in the figure given? For this
  particular JFET, IDSS 12mA and VGS(off) -3V.
• (Given ID 1.96mA)

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Solution
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Effect of an AC Load on Voltage Gain

• When a load is connected to an amplifiers output
  through a coupling capacitor as shown in figure
  5a
• The ac drain resistance is effectively RD in
  parallel with RL because the upper end of RD is
  at ac ground
• The equivalent circuit is shown in figure 5b
• The total ac drain resistance is
• The effect of RL is to reduce the unloaded
  voltage gain

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Figure 5 JFET amplifier and its ac equivalent
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Example 5

• If a 4.7 k? load resistor is ac coupled to the
  output of the amplifier in previous example, what
  is the resulting rms output voltage?

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Input Resistance

• The actual input resistance seen by the signal
  source is the gate-to-ground resistor, RG in
  parallel with the FETs input resistance
  VGS/IGSS.
• The reverse leakage current, IGSS is typically
  given on the data sheet for a specific value of
  VGS
• Therefore

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Example 6

• What is input resistance is seen by the signal
  source in the figure? Given IGSS30nA at VGS10V

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Solution
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D-MOSFET Amplifier Operation

• A zero-biased common-source n-channel D-MOSFET
  with an ac source capacitively coupled to the
  gate is shown in figure 6a.
• The gate is approximately 0Vdc and the source
  terminal is at ground, thus making VGS0V
• Signal voltage causes Vgs to swing above and
  below its zero value, producing a swing in Id
• The negative swing in Vgs, produce a depletion
  mode
• Thus, Id decrease
• The positive swing in Vgs produces the
  enhancement mode
• Thus, Id increase

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Figure 6a Zero-biased D-MOSFET common-source
amplifier
Figure 6b Depletion-enhancement operation of
D-MOSFET shown on transfer characteristic curve
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• Note that
• The enhancement mode is to the right of the
  vertical axis (VGS0)
• The depletion mode is to the left of the vertical
  axis
• The dc analysis
• IDIDSS at VGS0
• VDVDD-IDRD
• The ac analysis is the same as for the JFET
  amplifier

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Example 7

• The particular D-MOSFET used in the figure has
  an IDSS of 200mA and gm of 200mS. Determine both
  the dc drain voltage and ac output voltage.
  Vin500mV

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Solution
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E-MOSFET Amplifier Operation

• A common-source n-channel E-MOSFET with voltage
  divider bias with an ac source capacitively
  couple to the gate is shown in figure 7a
• The gate is biased with a positive voltage such
  that VGSgtVGS(th)
• As with JFET and D-MOSFET, the signal voltage
  produces a swing in Vgs above and below its
  Q-point value, VGSQ
• Causes a swing in Id above and below its Q-point
  value, IDQ (figure 7b)
• Operation is entirely in the enhancement mode

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Figure 7a Common-source E-MOSFET amplifier with
voltage-divider bias
Figure 7b E-MOSFET (n-channel) operation shown
on transfer characteristic curve
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• The circuit in figure 7a uses voltage divider
  bias to achieve a VGS above threshold
• The general dc analysis proceed as follows using
  the E-MOSFET characteristic equation to solve for
  ID
• The voltage gain expression is the same as for
  the JFET and D-MOSFET circuits
• The ac input resistance is

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Example 8

• Transfer characteristic curve for a particular
  n-channel JFET, D-MOSFET and E-MOSFET are shown
  in the figure. Determine the peak-to-peak
  variation an Id when Vgs is varied 1V about its
  Q-point value for each curve.

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Solution
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Example 9

• A common-source amplifier using an E-MOSFET is
  shown in the figure. Find VGS, ID, VDS and the ac
  output voltage. Assume that for this particular
  device, ID(on)200mA at VGS4V, VGS(th)2V and
  gm23mS. Vin25mV.

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COMMON-DRAIN AMPLIFIERS
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COMMON-DRAIN AMPLIFIERS

• A common-drain JFET amplifier is shown in figure
  8.
• Self-biasing is used in this particular circuit.
• The input signal is applied to the gate through a
  coupling capacitor, C1 and the output signal is
  coupled to the load resistor through C2
• There is no drain resistor.

Figure 8
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Voltage gain

• For the voltage follower in figure 9 is
• As in all amplifier, the voltage gain is
• Substituting
• Therefore

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Figure 9

• Notice that the gain is always slightly less than
  1.
• If gmRsgtgt1, then a good approximation is AV1.
• Since the output voltage is source, it is in
  phase with the gate (input) voltage.

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Input Resistance

• Because the input signal is applied to the gate
• The input resistance seen by the input signal
  source is extremely high. (just as in the
  common-source amplifier configuration)
• The gate resistor, RG in parallel with the input
  resistance looking in at the gate is the total
  input resistance.

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Example 10

• Determine the voltage gain of the amplifier in
  the figure using the data sheet in formation
  given. Also determine the input resistance. Use
  minimum data sheet values where available.

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Solution
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COMMON-GATE AMPLIFIERS
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COMMON-GATE AMPLIFIERS

• A self-biased common-gate amplifier is shown in
  figure 10.
• The gate is connected directly to ground.
• The input signal is applied at the source
  terminal through C1
• The output is coupled through C2 from the drain
  terminal.

Figure 10
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Voltage Gain

• The voltage gain from source to drain is develop
  as follows
• Notice that the gain expression is the same as
  for the common-source JFET amplifier.

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Input Resistance

• Both common-source and common drain
  configurations have extremely high input
  resistance
• Because the gate is the input terminal.
• In contrast, the common-gate configuration where
  the source is the input terminal has a low input
  resistance.

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Example 11

• Determine the minimum voltage gain and input
  resistance of the amplifier in figure given.

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Solution