Title: Multicast Parallel Pipeline Router Architecture for NetworkonChip
1Multicast Parallel Pipeline Router
Architecturefor Network-on-Chip
- Author Faizal A. Samman, Thomas Hollstein,
Manfred Glesner, - Speaker ???
- DATE,2008
2About this paper
- Present a flexible mesh router architecture
supporting unicast and multicast service - A flexible mechanism to manage broadcast flow
3Introduction
- By the end of this decade, the transistor feature
size will be 50-nm and it operates below one
volt. requirements and should be scalable for
wide range. (ITRS) - SoCs will grow to 4-billion transistors running
at 10 GHz. - A limiting factor for the performance, and energy
consumption will be on-chip physical
interconnections
4Introduction
- Networks-on-Chip provide advanced intellectual
properties IP communication concepts for SoCs - Sharing the wires between several communication
- flows makes the use of the wires more efficient
5Traditional 4X4 mesh NOC topology
6NoC design principle
- The architecture and routing decision must meet
bandwidth requirements and should be scalable for
wide range - of applications
- For example
- Network topology could influence the scalability
and performance
7Synchronous /Asynchronous design
- Synchronous
- Extra clock power consumption
- electromagnetic interference effect
- Asynchronous
- A promising concept
- lacks of industrial standard support, especially
with respect to testability issues
8General router architecture for XHiNoC
- Port
- FIFO
- Routing engine
- ID manager
- Link state controller
9Packet format
- Using 3 bits to record packet type (header ,body
,tail) - Using 3 bits to record local id number to
differentiate it from another
10Multicast procedure
- Forwarding Header Flits
- A header flit by a header flit
- Record the direction based on its ID in
registers - Broadcasting Payload Flits
- Each time a flit appears in the FIFO output, the
LUT (look up table ) will check its ID to find
its directions in the routing table
11ID-tag-basedMulticast Routing
- Two issues
- Packet flows are controlled based on ID-tags
- All flits of a packet have the same ID-tag on a
certain communication link
12ID-tag-basedMulticast Routing
Routing engine
13Packet Identity Management
- IDM
- IDM Update new ID for new packet flowing through
the outport. - Guarantee that different packets will have a
different ID-tag. - Stop forwarding when IDs is run out.
- Delete all information about a certain ID when
the tail flit flows through IDM
14Synchronous Parallel Pipelined Switching
15Synchronous Parallel Pipelined Switching
- 1st cycle RE sends direction request signals to
the LCFS - 2nd cycle The arbiter in the LCFS has selected
the winner to access the outport by sending a
grant
16Multicast Broadcast-flow Management
- LCFS(Link Controller and Flow supervisor)
- Three major part
- DecMC unit decodes 3-bit routing direction
request signals from all inports into 1-bit
signals. - arbiter is in charge of selecting a winner of all
the requests - GMC is in charge of granting the FIFO
17Multicast Broadcast-flow Management
18Multicast Broadcast-flow Management
- Why forwarding
- For instance
- When one of the direction is not win the
arbitraction - Using forwarding could reset the successful way
to avoid the flit being forwarded more than once
into the same outport -
19Broadcast-FlowManagement
20Experiment Results
- Experiment setting
- injecting 2 multicast packets,which have 7
destinations in 2-D 4x4 mesh topology. - Each packet consists of 128 flits,it means, that
each packet header is followed by 121 payload
flits - Traffic scenarios
21Experiment Results
22Experiment Results
- By using UMC 180nm standard-cell technology
- The XHiNoC can be run at 230 MHz. Total number of
logic cells is 10577. Migrating from unicast to
multicast with - The same XY routing algorithm increases 15 of
total logic cells using unicast service (9201
logic cells). Five FIFO buffers occupy 44 of
total cell area
23Conclusion and future work
- Propose a new mechanism to serve multicast packet
- For future works
- Adaptive routing algorithms