Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability

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Metrics for Reconfigurable Architectures
Characterization Remanence and Scalability

• Pascal BENOIT
• G. Sassatelli L. Torres D. Demigny M. Robert
  G. Cambon

Name.Surname_at_lirmm.fr
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Outline

• Context
• Remanence
• Operative Density
• Case Study the Systolic Ring
• Conclusion and perspectives

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Context

• SoC and Customizable Platform Based-Design

DSP
Reconfigurable Hardware (Fine Grain)
Specifications Processing power Area Power
consumption etc.
ASIC 2
Reconfigurable Hardware (Coarse Grain)
ASIC 1
We need metrics to compare !
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Context

• Architecture characterization
• Processing power
• Power consumption
• Flexibility
• Parallelism potential
• Dynamism
• Silicon area
• Scalability
• Metrics
• Dehon criterion
• Remanence
• Operative density

Generalisation to Architectural
model characterisation and metrics depend on
architectural parameters
 Comparing architectures with a minimum of
criteria 
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Remanence

• Definition
• NPE of processing elements (PE) Nc of PE
  configurable per cycle
• Fe operating frequency Fc configuration
  frequency
• Characterizes the Dynamism
• of cycles to (re)configure the whole
  architecture
• Amount of data to compute between 2 configurations

Fc
Fe
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Remanence

• Comparisons
• Only 1 cycle to (re)configure the DSP
• Few cycles to (re)configure coarse grain RA (?8)
• Many cycles to (re)configure fine grain RA

NPE
Nc
R
Name
Type
F (MHz)
2304
0.14
16457
ARDOISE
Fine Grain RA
33
128
16
8
MorphoSys
Coarse Grain RA
100
24
4
6
Systolic Ring
Coarse Grain RA
200
24
4
6
DART
Coarse Grain RA
130
TMS320C62
DSP VLIW
8
8
300
1
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Operative Density

• Definition
• NPE of PE A Core Area (relative unit ?²)
• Area can be expressed as a function of NPE
  (architectural model)
• Characterizes
• Fixed NPE
• of operators per relative area unit
• Variable NPE
• OD as a function of NPE
• A(NPE) NPEAPEAinterconnect(NPE)Amemory(NPE)
  Asequencer(NPE)
• OD(NPE) k ? A(NPE) k.NPE ? the architectural
  model is scalable

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Operative Density

• Comparisons
• DSP sequencer area
• ARDOISE fine granularity
• Coarse granularity
• Reconfigurable architectures
• Scalabilty of interconnect resources ?
• Generalization to architectural models

Name
Type
l
Name
Type
l
Area(M
²
)
Area(M
²
)
NPE
OD (NPE)
ARDOISE
0.2
ARDOISE
0.2
Fine Grain RA
26
12300
Fine Grain RA
26
12300
Systolic Ring (S1, C6, N2)
4.8
Systolic Ring (S1, C6, N2)
4.8
Coarse Grain RA
24
500
Coarse Grain RA
24
500
DART
8.0
DART
8.0
Coarse Grain RA
24
300
Coarse Grain RA
24
300
Systolic Ring (S1, C16, N4)
Coarse Grain RA
128
7600
1.7
Systolic Ring (S1, C16, N4)
Coarse Grain RA
128
7600
1.7
MorphoSys
Coarse Grain RA
128
5500
2.3
MorphoSys
Coarse Grain RA
128
5500
2.3
TMS320C62
DSP VLIW
8
12300
0.1
TMS320C62
DSP VLIW
8
12300
0.1
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• Architectural Model Characterization - A Case
  Study
• The Systolic Ring

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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE

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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths

Dnode
Dnode
Dnode
Dnode
Dnode
Dnode
Dnode
Dnode
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer

layer 1
Dnode
Dnode
layer 4
Dnode
Dnode
Dnode
Dnode
layer 2
Dnode
of layers 4 (C 4) of Dnode per layer 2
(N 2)
Dnode
layer 3
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer

layer 1
layer 2
layer 3
layer 8
layer 4
layer 7
of layers 8 (C 8) of Dnode per layer 2
(N 2)
layer 5
layer 6
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer
• S of Rings

layer 1
layer 2
layer 3
layer 8
layer 4
layer 7
of layers 8 (C 8) of Dnode per layer 2
(N 2) 1 Systolic Ring (S 1)
layer 5
layer 6
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer
• S of Rings

of layers 4 (C 4) of Dnode per layer 2
(N 2) 4 Systolic Ring (S 4)
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer
• S of Rings
• Control Units
• Local Dnodes units

Dnode Sequencer
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer
• S of Rings
• Control Units
• Local Dnode unit
• Local Ring unit

Local Ring Sequencer
Local Ring Sequencer
Local Ring Sequencer
Local Ring Sequencer
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Architectural model Characterization

• The Systolic Ring Architectural model
• Based on a coarse-grained configurable PE
• Circular datapaths
• 3 parameters
• C of layers
• N of Dnodes per layer
• S of Rings
• Control Units
• Local Dnode unit
• Local Ring unit
• Global unit

Global Sequencer
Local Ring Sequencer
Local Ring Sequencer
Local Ring Sequencer
Local Ring Sequencer
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Architectural model Characterization

• Remanence
• Only one Systolic Ring S1
• NPE of Dnodes NCS NC
• Remanence formalisation
• k C/N

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Architectural model Characterization

• A(NPE) formalisation for OD(NPE)
• 0.18µ CMOS technology
• C 4, N 2, S 1
• A(8) 3.3 mm ²
• A(8) 407M ? ²
• Area formalisation
• A ( NPE ) f ( N, C, S )
• depends on C / N ratio and S
• NPE N.C.S

Systolic Ring layout (C4, N2, S1)
Area formalisation calibrated on these results
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Architectural model Characterization

• OD(NPE) for 1 Systolic Ring (S1)
• k C/N 0.25 4
• decreasing OD(NPE)
• OD(NPE) for several Systolic Ring
• k C/N 4
• multi-ring instanciations increase scalability

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Architectural model Characterization

• Customisation and design technique
• between 60 and 80 processing elements

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Architectural model Characterization

• Customisation and design technique
• between 60 and 80 processing elements

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Architectural model Characterization

• Customisation and design technique

Design Space
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Architectural model Characterization
Best OD and remanence Worst interconnect
resources and processing power
Design Space
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Architectural model Characterization
Worst OD and remanence Best interconnect
resources and processing power
Design Space
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Architectural model Characterization
R and OD can be integrated in CAD tools to
observe architectural parameters effects and
choose best trade-offs in the design space
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Conclusion and perspectives
IP 1
IP 2
IP 3
IP n
R1 OD1
R2 OD2
R3 OD3
Rn ODn
Specifications Processing power Area Power
consumption etc.
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Conclusion and perspectives
IP 1
IP 2
IP 3
IP n
R1 OD1
R2 OD2
R3 OD3
Rn ODn
Architectural models Comparisons
Specifications Processing power Area Power
consumption etc.
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Conclusion and perspectives
IP 1
IP 2
IP 3
IP n
R1 OD1
R2 OD2
R3 OD3
Rn ODn
Architectural model Customisation
Specifications Processing power Area Power
consumption etc.
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Thank You