ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller

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ECE 361Computer ArchitectureLecture 11
Designing a Multiple Cycle Controller
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Review of a Multiple Cycle Implementation

• The root of the single cycle processors
  problems
• The cycle time has to be long enough for the
  slowest instruction
• Solution
• Break the instruction into smaller steps
• Execute each step (instead of the entire
  instruction) in one cycle
• Cycle time time it takes to execute the longest
  step
• Keep all the steps to have similar length
• This is the essence of the multiple cycle
  processor
• The advantages of the multiple cycle processor
• Cycle time is much shorter
• Different instructions take different number of
  cycles to complete
• Load takes five cycles
• Jump only takes three cycles
• Allows a functional unit to be used more than
  once per instruction

3
Review Instruction Fetch Cycle, In the Beginning

• Every cycle begins right AFTER the clock tick
• memPC PClt310gt 4

Clk
One Logic Clock Cycle
You are here!
PCWr?
PC
32
MemWr?
IRWr?
32
32
RAdr
Clk
4
32
Ideal Memory
Instruction Reg
WrAdr
32
Dout
Din
32
ALUop?
32
Clk
4
Review Instruction Fetch Cycle, The End

• Every cycle ends AT the next clock tick (storage
  element updates)
• IR lt-- memPC PClt310gt lt-- PClt310gt 4

Clk
One Logic Clock Cycle
You are here!
PCWr1
PC
32
MemWr0
IRWr1
32
00
32
RAdr
Clk
4
32
Ideal Memory
Instruction Reg
32
WrAdr
Dout
Din
ALUOp Add
32
32
Clk
5
Putting it all together Multiple Cycle Datapath
PCWr
PCWrCond
PCSrc
BrWr
Zero
ALUSelA
MemWr
IRWr
RegWr
RegDst
IorD
1
Mux
32
PC
0
32
Zero
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
Ideal Memory
32
Instruction Reg
Reg File
5
32
4
Rt
0
32
Rw
WrAdr
32
1
32
Rd
Din
Dout
busW
32
busB
2
32
3
Imm
32
ALUOp
MemtoReg
ExtOp
ALUSelB
6
Instruction Fetch Cycle Overall Picture
PCWr1
PCWrCondx
PCSrc0
BrWr0
Zero
ALUSelA0
MemWr0
IRWr1
IorD0
1
Mux
32
PC
0
32
Zero
RAdr
32
32
busA
Ideal Memory
32
Instruction Reg
32
4
0
32
WrAdr
32
1
32
Din
Dout
32
busB
2
32
3
ALUSelB00
ALUOpAdd
7
Register Fetch / Instruction Decode (Continue)

• busA lt- Regrs busB lt- Regrt
• Target lt- PC SignExt(Imm16)4

PCWr0
PCWrCond0
PCSrcx
BrWr1
Zero
ALUSelA0
MemWr0
IRWr0
RegWr0
RegDstx
IorDx
1
Mux
32
PC
0
32
Zero
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
Ideal Memory
32
Instruction Reg
Reg File
5
32
4
Rt
0
32
Rw
WrAdr
32
1
32
32
Rd
Din
Dout
busW
32
busB
2
32
3
Control
Beq
Op
Imm
Rtype
6
ALUSelB10
Func
Ori
16
32
6
Memory
ALUOpAdd

ExtOp1
8
R-type Execution

• ALU Output lt- busA op busB

PCWr0
PCWrCond0
PCSrcx
BrWr0
Zero
ALUSelA1
MemWr0
IRWr0
RegWr0
RegDst1
IorDx
1
Mux
32
PC
0
32
Zero
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
Ideal Memory
32
Instruction Reg
Reg File
5
32
4
Rt
0
32
Rw
WrAdr
32
1
32
32
Rd
Din
Dout
busW
32
busB
2
32
3
Imm
32
ALUOpRtype
MemtoRegx
ExtOpx
ALUSelB01
9
R-type Completion

• Rrd lt- ALU Output

PCWr0
PCWrCond0
PCSrcx
BrWr0
Zero
ALUSelA1
MemWr0
IRWr0
RegWr1
RegDst1
IorDx
1
Mux
32
PC
0
32
Zero
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
Ideal Memory
32
Instruction Reg
Reg File
5
32
4
Rt
0
32
Rw
WrAdr
32
1
32
Rd
Din
Dout
busW
32
busB
2
32
3
Imm
32
ALUOpRtype
MemtoReg0
ExtOpx
ALUSelB01
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Outline of Todays Lecture

• Recap
• Review of FSM control
• From Finite State Diagrams to Microprogramming

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Overview

• Control may be designed using one of several
  initial representations. The choice of sequence
  control, and how logic is represented, can then
  be determined independently the control can then
  be implemented with one of several methods using
  a structured logic technique.
• Initial Representation Finite State Diagram
  Microprogram
• Sequencing Control Explicit Next State
  Microprogram counter Function Dispatch ROMs
  
• Logic Representation Logic Equations Truth Tables
• Implementation Technique PLA ROM

hardwired control
microprogrammed control
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Initial Representation Finite State Diagram
0
1
8
beq
2
AdrCal
1 ExtOp
ALUSelA
ALUSelB11
lw or sw
ALUOpAdd
x MemtoReg
Ori
PCSrc
10
Rtype
OriExec
lw
sw
6
3
5
SWMem
LWmem
1 ExtOp
1 ExtOp
ALUSelA, IorD
MemWr
ALUSelB11
ALUSelA
ALUOpAdd
ALUSelB11
ALUOpAdd
x MemtoReg
PCSrc
x PCSrc,RegDst
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MemtoReg
OriFinish
7
4
LWwr
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Sequencing Control Explicit Next State Function
O u t p u t s
Control Logic
Multicycle Datapath
Inputs
State Reg

• Next state number is encoded just like datapath
  controls

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Logic Representative Logic Equations

• Alternatively, prior state condition
• S4, S5, S7, S8, S9, S11 -gt State0
• _________________ -gt State 1
• _________________ -gt State 2
• _________________ -gt State 3
• _________________ -gt State 4
• State2 op sw -gt State 5
• _________________ -gt State 6
• State 6 -gt State 7
• _________________ -gt State 8
• State2 op jmp -gt State 9
• _________________ -gt State 10
• State 10 -gt State 11

• Next state from current state
• State 0 -gt State1
• State 1 -gt S2, S6, S8, S10
• State 2 -gt__________
• State 3 -gt__________
• State 4 -gtState 0
• State 5 -gt State 0
• State 6 -gt State 7
• State 7 -gt State 0
• State 8 -gt State 0
• State 9-gt State 0
• State 10 -gt State 11
• State 11 -gt State 0

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Implementation Technique Programmed Logic Arrays

• Each output line the logical OR of logical AND of
  input lines or their complement AND minterms
  specified in top AND plane, OR sums specified in
  bottom OR plane

Op5
R 000000 beq 000100 lw 100011 sw
101011 ori 001011 jmp 000010
Op4
Op3
Op2
Op1
Op0
6 0110 7 0111 8 1000 9 1001 10 1010 11
1011
0 0000 1 0001 2 0010 3 0011 4 0100 5
0101
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Implementation Technique Programmed Logic Arrays

• Each output line the logical OR of logical AND of
  input lines or their complement AND minterms
  specified in top AND plane, OR sums specified in
  bottom OR plane

lw 100011 sw 101011 R 000000 ori
001011 beq 000100 jmp 000010
Op5
Op4
Op3
Op2
Op1
Op0
0 0000 1 0001 2 0010 3 0011 4 0100 5
0101
6 0110 7 0111 8 1000 9 1001 10 1010 11
1011
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Multicycle Control

• Given numbers of FSM, can turn determine next
  state as function of inputs, including current
  state
• Turn these into Boolean equations for each bit of
  the next state lines
• Can implement easily using PLA
• What if many more states, many more conditions?
• What if need to add a state?

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Next Iteration Using Sequencer for Next State

• Before Explicit Next State Next try variation 1
  step from right hand side
• Few sequential states in small FSM suppose added
  floating point?
• Still need to go to non-sequential states e.g.,
  state 1 gt 2, 6, 8, 10
• Initial Representation Finite State Diagram
  Microprogram
• Sequencing Control Explicit Next State
  Microprogram counter Function Dispatch ROMs
  
• Logic Representation Logic Equations Truth Tables
• Implementation Technique PLA ROM

hardwired control
microprogrammed control
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Sequencer-based control unit
Control Logic
Multicycle Datapath
Outputs
Inputs
Types of branching Set state to 0 Dispatch
(state 1 2) Use incremented state number
1
Adder
Address Select Logic
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Sequencer-based control unit details
Control Logic
Inputs
Dispatch ROM 1 Op Name State 000000 Rtype 0110000
010 jmp 1001000100 beq 1000001011 ori 1010
100011 lw 0010101011 sw 0010 Dispatch ROM
2 Op Name State 100011 lw 0011101011 sw 0101
1
Adder
Mux
3
0
1
2
0
Address Select Logic
ROM2
ROM1
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Implementing Control with a ROM

• Instead of a PLA, use a ROM with one word per
  state (Control word)
• State number Control Word Bits 18-2 Control
  Word Bits 1-0
• 0 10010100000001000 11 1
  00000000010011000 01 2 00000000000010100 10
  3 00110000000010100 11 4 00110010000010110 00
  5 00101000000010100 00 6
  00000000001000100 11 7 00000000001000111 00
  8 01000000100100100 00 9 10000001000000000 00
  10 11 11 00

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Next Iteration Using Microprogram for
Representation

• Initial Representation Finite State Diagram
  Microprogram
• Sequencing Control Explicit Next State
  Microprogram counter Function Dispatch ROMs
  
• Logic Representation Logic Equations Truth Tables
• Implementation Technique PLA ROM
• ROM can be thought of as a sequence of control
  words
• Control word can be thought of as instruction
  microinstruction
• Rather than program in binary, use assembly
  language

hardwired control
microprogrammed control
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Microprogramming

• Control is the hard part of processor design
• Datapath is fairly regular and well-organized
• Memory is highly regular
• Control is irregular and global

Microprogramming -- A Particular Strategy for
Implementing the Control Unit of a processor
by "programming" at the level of register
transfer operations Microarchitecture --
Logical structure and functional capabilities of
the hardware as seen by the microprogrammer
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Macroinstruction Interpretation
User program plus Data this can change!
Main Memory
ADD SUB AND
. . .
one of these is mapped into one of these
DATA
execution unit
AND microsequence e.g., Fetch Calc
Operand Addr Fetch Operand(s)
Calculate Save Answer(s)
control memory
CPU
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Microprogramming Pros and Cons

• Ease of design
• Flexibility
• Easy to adapt to changes in organization, timing,
  technology
• Can make changes late in design cycle, or even in
  the field
• Can implement very powerful instruction sets
  (just more control memory)
• Generality
• Can implement multiple instruction sets on same
  machine.
• Can tailor instruction set to application.
• Compatibility
• Many organizations, same instruction set
• Costly to implement
• Slow

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Summary Multicycle Control

• Microprogramming and hardwired control have many
  similarities, perhaps biggest difference is
  initial representation and ease of change of
  implementation, with ROM generally being easier
  than PLA
• Initial Representation Finite State Diagram
  Microprogram
• Sequencing Control Explicit Next State
  Microprogram counter Function Dispatch ROMs
  
• Logic Representation Logic Equations Truth Tables
• Implementation Technique PLA ROM

hardwired control
microprogrammed control