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RF CIRCUITS

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Bob Frye. Andrei Vladimirescu. W-CDMA Transmitter/Receiver. Q. DAC. PA. I. PLL. DAC. 2 GHz ... Which type of DAC to implement? Binary weighted, unit element, segmented ... – PowerPoint PPT presentation

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Title: RF CIRCUITS


1
RF CIRCUITS
2
Session Participants
  • Sayf Alalusi
  • Sam Blackman
  • Chinh Doan
  • Brian Limketkai
  • Ian ODonnell
  • David Sobel
  • Johan Vanderhaegen
  • Dennis Yee
  • Robert Brodersen
  • Ali Niknejad
  • Manolis Terrovitis
  • Robert Meyer
  • Bob Frye
  • Andrei Vladimirescu

3
W-CDMA Transmitter/Receiver
Basestation Transmitter
I
DAC
PA
Q
DAC
2 GHz
PLL
Mobile Receiver
I
ADC
LNA
ADC
Q
PLL
4
Transmitter DAC
I
DAC
Q
DAC
  • DAC specifications
  • 8 bits
  • 100 MHz

Sam Blackman
  • Design decisions
  • Which type of DAC to implement?
  • Binary weighted, unit element, segmented
  • Is matching going to be a problem?
  • How about SNR?

5
Transmitter LPF/Mixer
Johan Vanderhaegen
  • LPF 2nd order Butterworth, f3db25MHz
  • Mixer Gilbert cell
  • I and Q channel are added in the current domain

6
Wherefore 50W?
  • Originally a trade-off for coax cables
  • Maximum power handling at 30W
  • Minimum attenuation at 77W
  • Is 50W still a good choice?
  • Can the antenna operate correctly when its
    terminals are open-circuited?
  • Can we design an on-board filter that has
    open-circuited terminals?

2 GHz
Ian ODonnell
Sayf Alalusi
7
PLL
I
ADC
LNA
ADC
Q
Chinh Doan
PLL
  • Frequency synthesizer requirements
  • Fixed frequency for direct downconversion
  • Processing gain reduces effect of reciprocal
    mixing
  • Correlation decreases RMS phase noise
  • Relaxed requirements low power, fully
    integrated, CMOS implementation

8
Receiver Mixer
  • Relaxed requirements allow for simpler designs
    consuming less power
  • Switch sizes are kept small thus removing the
    need for an LO buffer
  • Increased flicker noise due to small switches in
    the active mixer
  • No flicker noise in passive mixer

9
Receiver ADC
I
ADC
LNA
ADC
Q
PLL
David Sobel
  • Specifications SNDR 62 dB, fNYQ25 Ms/s
  • ?D modulator
  • 2-1-1 multi-bit cascade for low-OSR solution
  • Projected total power dissipation lt10-15 mW
  • ?D-assisted timing recovery

10
Monolithic Passive Devices
  • ASITIC software
  • Example circuits
  • VCO
  • PA

Ali Niknejad
11
Active CMOS Mixer Analysis
  • Objective Analytical Design Methodology
  • Noise Calculate noise contribution from all
    internal and external noise sources
  • Intermodulation Distortion Fast evaluation of
    the intermodulation of the switching pair
  • Express performance in terms of simple
    expressions and graphs of normalized parameters

Manolis Terrovitis
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