Instruction Cycles

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Instruction Cycles Machine Cycles (Bus Cycles) T
States. Calculating Execution Times of
instructions
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(No Transcript)
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INSTRUCTION CYCLE
T State
T1
T2
T3
T1
T2
T3
T1
T2
T3
T4
T1
M1
M2
M3
MEMORY READ CYCLE
OPCODE FETCH CYCLE
MEMORY WRITE CYCLE
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INSTRUCTION CYCLE
T State
T1
T2
T3
T1
T2
T3
T1
T2
T3
T4
T1
M1
M2
M3
MEMORY READ CYCLE
OPCODE FETCH CYCLE
MEMORY READ CYCLE
LD HL, 0x1850 OPCODE 0x21 OPCODE FETCH
CYCLE OPERAND1 0x50
MEMORY READ CYCLE
OPERAND2 0x18 MEMORY READ CYCLE M CYCLES 3,
T STATES 10, 4 MHz EXEC.TIME 2.50 uS
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System Control
Address Bus
CPU Control
CPU Bus Control
Data Bus
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M1 Cycle
T1
T2
T3
T4
CLOCK
PC
Refresh Addr.
A0 - A15
/MREQ
/RD
INST
D0-D7
7
Memory Read Cycle
T1
T2
T3
CLOCK
A0 - A15
MEMORY ADDRESS
/MREQ
/RD
D0 - D7
Data IN
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Memory Write Cycle
T1
T2
T3
CLOCK
A0 - A15
MEMORY ADDRESS
/MREQ
/WR
D0 - D7
DATA OUT