Timing Override Verification TOV

1
Timing Override Verification (TOV)

• Erik Seligman
• CS 510, Lecture 18, March 2009

2
Agenda

• What is Timing Override Verification (TOV)?
• Multicycle Paths
• False Paths
• Deploying TOV Methods

3
Agenda

• What is Timing Override Verification (TOV)?
• Multicycle Paths
• False Paths
• Deploying TOV Methods

4
Review Timing Closure
f1 -gt f3 900ps f2 -gt f3 2700ps
data2
f1
ck
f3
data1
f2
out1
ck

• Check delays of all paths
• Signals must be fast enough for frequency
• Flag paths that miss, make circuit changes

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Do We Care About All Paths?

• Timing overrides relax checking of path
• Multicycle Path May take gt1 clk cycle
• Often due to crossing to slower clk domain
• May be consequence of logic
• False Path Infinite time allowed
• Path never matters logically
• Usually specify in SDC format
• set multicycle path ltngt -from -to
• set false path from -to

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Dangers of Timing Overrides

• What if false or multicycle path is wrong?
• i.e., logically not really false / multicycle
• Chip will not meet frequency
• Long path operates incorrectly
• Must slow down clock for proper function
• ? Important to verify!

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Verifying Timing Overrides

• Often ad hoc designer inspect manually
• Better create assertions
• Since SDCs manual, designer can create
• Introduce as requirement on design team!
• Can automate to some extent with scripts
• Generally hard to FPV
• Cross top-level blocks, specified at netlist
• CAD tools
• Fishtail, RealIntent, Atrenta, BluePearl
• Some claim specialized FPV engines
• Optimized to be able to prove SDCs

8
Agenda

• What is Timing Override Verification (TOV)?
• Multicycle Paths
• False Paths
• Deploying TOV Methods

9
Multicycle Path
ck is 3x freq of ck2
n1
f3
data1
f2
out1
ck
ck2

• set_multicycle_path 3 from f2 to f3
• What assertions might help verify?

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Multicycle Path
ck is 3x freq of ck2
n1
f3
data1
f2
out1
ck
ck2

• set_multicycle_path 3 from f2 to f3
• What assertions might help verify?
• Value at f2 is always held 3 cycles (or 4)?
• And ?

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Multicycle Path
ck is 3x freq of ck2
n1
f3
data1
f2
out1
ck
ck2

• set_multicycle_path 3 from f2 to f3
• What is needed for this to be valid?
• Value at f2 is always held 3 cycles
• f2 transition ? stable 3 cycles before some ck2
  capture edge

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Be careful about capture edge!
ck
ck2
bad_data
good_data

• set_multicycle_path 3 from f2 to f3
• Bad data is stable for a long time
• But never stable 3 cycles before capture edge

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Sensitization Issue
ck is 3x freq of ck2
n1
f3
data1
f2
out1
ck
ck2

• set_multicycle_path 3 from f2 to f3
• OR rather than XOR change situation?

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Sensitization Issue
1
ck is 3x freq of ck2
n1
f3
data1
f2
out1
ck
ck2

• set_multicycle_path 3 from f2 to f3
• OR rather than XOR change situation?
• Path may not be sensitized
• In general case, may need to check this condition

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General Multicycle Assertion

• Important conditions
• Input flop to path transitions
• Path sensitized
• not masked by mux or ORed with 1, for example
• Destination flop samples
• Key assertion
• (Dest samples sensitized) ? (!Transition for
  last ltngt cycles)

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Agenda

• What is Timing Override Verification (TOV)?
• Multicycle Paths
• False Paths
• Deploying TOV Methods

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False Path Example
s1
d2
s2
n1
f3
data1
f2
out1
ck

• set_false_path from f2 to f3
• What assertions would be useful here?

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False Path Example
s1
d2
s2
n1
f3
data1
f2
out1
ck

• set_false_path from f2 to f3
• What assertions would be useful here?
• Path never sensitized !(s10 s21)
• Any others?

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False Path Example
s1
d2
s2
n1
f3
data1
f2
out1
ck

• set_false_path from f2 to f3
• What assertions would be useful here?
• Path never sensitized !(s10 s21)
• Sensitization condition correct
• (!(s10 s21))2 0 stable(d2) -gt
  stable(n1)
• (if not sensitized other inputs stable ?
  output stable)

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False Path Example
s1
d2
s2
n1
f3
data1
f2
out1
ck

• set_false_path from f2 to f3
• What assertions would be useful here?
• Path never sensitized !(s10 s21)
• Sensitization condition correct
• (!(s10 s21))2 0 stable(d2) -gt
  stable(n1)
• (if not sensitized other inputs stable ?
  output stable)
• Or just stable(d2) -gt stable(n1)?

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Agenda

• What is Timing Override Verification (TOV)?
• Multicycle Paths
• False Paths
• Deploying TOV Methods

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Generating TOV Asserts

• Simple method Designers write
• Designers write SDCs, so know design
• Low overhead to introduce
• May not be accurate, complete
• CAD tools
• Automatic
• - Additional tool in flow is output saved?
• - May be noisy

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Checking TOV Asserts

• Simulation
• Automatic if asserts added to RTL
• Depends on test suite
• FPV
• High confidence, fuller coverage
• - Hard to prove
• - often specified at top level of large blocks
• - (vendors claim specialized engines)

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One more wrinkle

• Designers generate SDCs on netlists
• Not on RTL
• Assertions involve non-rtl signals
• Solutions?
• DEs can manually convert to RTL asserts
• Should be late in project, FEV mapping available
• Tool solutions Fishtail refocus
• Generate check asserts on netlist
• Gate-level simulation

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Other Complications

• -through exceptions?
• Make asserts more complex ensure that through
  node is controlling transition when checking
• Multicycle path at asynchronous CDC
• Bad luck might hit metastability window
• Be careful to hold value an extra cycle

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A Further Opportunity

• Auto-identify false/multicycle paths?
• Capability in some tools (Fishtail, RealIntent)
• Both identify and prove the paths
• Lots of TOVs ? easier to close timing
• But is this too risky?
• Tools get thousands of these paths
• DEs nervous if unreviewed paths in design
• Low impact on timing closure
• Small set of critical paths are what matter
• ? Few design teams adopt auto-TOV methods

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Conclusions

• Multicycle / False paths are risky
• But needed for timing closure
• Can generate asserts for safety
• Several choices in strategy
• Manual asserts or CAD tool
• Simulation or formal
• RTL or netlist level
• Plenty of reasonable sets of choices give much
  increased level of TOV confidence!

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References / Further Reading

• http//www.fishtail-da.com/
• http//www.realintent.com/
• http//www.atrenta.com/solutions/products/spyglass
  _constraints.htm
• http//www.bluepearlsoftware.com/products/cobalt.h
  tml
• http//www.chipdesignmag.com/display.php?articleId
  1136issueId21