Title: Implementing CAMs In Stratix JeanMichel Vuillamy Altera Europe South
1Implementing CAMs In StratixJean-Michel
VuillamyAltera Europe South
2Agenda
- Introduction
- Targeted CAM for Stratix
- Stratix Fast CAM Implementation
- Other Possible Stratix CAM Implementations
- Conclusions
- Appendix
3Introduction
4Introduction
- APEX 20KE/C, APEX II Mercury Embedded System
Blocks (ESBs) Have Native Support of Content
Addressable Memory (CAMs) - Stratix M512, M4K MegaRAM Blocks Do Not Have
Native CAM Support - Although Decision Not To Natively Support CAMs in
Stratix May Appear As A Step Back, This
Presentation Clearly Demonstrates It Is Not - Main Objective Is To Describe Possible (
Realistic) Implementations of CAMs in Stratix
5Targeted CAM for Stratix
6Targeted CAM - Description
- Timings
- Single-Cycle Write Operation
- Single-Cycle Match Operation
- Address Format
- Encoded Write Address
- Unencoded Match Address
- Encoded Match Address Can Be Derived W/ Extra
Additional Logic - Ternary CAMs Not Supported
7Targeted CAM - Logical Symbol
8Targeted CAM - Port Description
9Targeted CAM - Example
- 32-Word CAM, 7-Bit Wide
- Operations Assuming CAM Is Initialized w/
Zeroes - Writing 0x1A _at_ 0x04, And Then Matching 0x1A,
MatchAddress Outputs 00000000 00000000 00000000
00010000 - 1 Located At Position 4 Of Bus
MatchAddress31..0
10Stratix Fast CAM Implementation
11Emulating CAM w/ RAM Principles
- CAM Can Be Emulated w/ RAM No Additional Logic
- Requires Simple Dual Port Memory
- Requires RAM w/ Mixed-Width Configuration Support
- Assuming A 2M-Word N-Bit Wide CAM, The Simple
Dual Port RAM Should Be Configured As Follows - RAM Write Port w/ 1-Bit Data
- Hooked to wrdelete_n CAM Control Input
- RAM Write Port w/ NM-Bit Address
- Hooked To Concatenation of Both N-Bit CAM Write
Data M-Bit CAM Write Address Busses - RAM Read Port w/ N-Bit Address
- Hooked To N-Bit CAM Data To Be Matched
- RAM Read Port w/ 2M-Bit Output Data Bus
- Hooked to 2M-Bit CAM Unencoded Match Resulting
Address
12Emulating CAM w/ RAM - Principles
- Key Ideas Behing the CAM Emulation Scheme w/ RAM
Are - Using The CAM Match Data For The RAM Read Address
- Writing The Right Unencoded Address Into The RAM
When Writing the CAM Write Data At The CAM Write
Address - Benefits
- Easy To Implement
- Extremely Fast (gt 300Mhz)
- Drawbacks
- Non Optimal Usage of Embedded Memory Bits.
However, This May Not Be An Issue Since Stratix
Has A Lot Of M512/M4K RAM Blocks
13Emulating CAM w/ RAM - Schematics
14Emulating CAM w/ Stratix M512 RAM Block
- Stratix Datasheet (Apr. 2002, ver. 2.0) Table 8
Page 31 - M512 Can Emulate - w/o Additional Logic Elements
- 16-Word 5-Bit Wide CAM,
- 8-Word 6-Bit Wide CAM, Or
- 4-Word 7-Bit Wide CAM
15Emulating CAM w/ Stratix M4K RAM Block
- Stratix Datasheet (Apr. 2002, ver. 2.0) Table 9
Page 35 - M4K Can Emulate - w/o Additional Logic Elements
- 32-Word 7-Bit Wide CAM,
- 16-Word 8-Bit Wide CAM,
- 8-Word 9-Bit Wide CAM, Or
- 4-Word 10-Bit Wide CAM
16Managing Deeper And/Or Wider CAMs
- Deeper CAMs Can Be Built Using Several M512/M4K
RAM Blocks - Additional Logic Required To Decode Write Address
MSB(s) Appropriately Drive Each M512/M4K Write
Enable Control Signals - Wider CAMs Can Be Built Using Several M512/M4K
RAM Blocks - Additional Logic Required In Order To AND
MatchAddress Results From Each M512/M4K
17 32-Word 5-Bit Wide CAM w/ 2 M512
18 32-Word 14-Bit Wide CAM w/ 2 M4K
19Other Possible Stratix CAM Implementations
20Other Possible CAM Implementations
- Assuming 2M-Word N-Bit Wide CAM, Consider Using
Stratix MegaRAM - Brute Force Approach Go Sequentially Through 2M
Words Stored In MegaRAM Compare Them Against
Data To Match - Takes 2M Clock Cycles (gt 300Mhz)
- Total Search Time Can Be Reduced By Taking
Advantage of the MegaRAM Wide Data Bus
Configurations - If K N-Bit Words Can Be Read From MegaRAM Block
in 1 Clock Cycle, Total Search Time Can Be
Divided By K At The Expense Of K Comparators - To Be Completed Later
21Conclusions
22Conclusions
- Stratix Does Support Fast CAM Implementation
Through Emulation - Search Can Be Performed In One Clock Cycle (gt
300Mhz) - 1 M512 RAM Block Can Emulate 16-Word 5-Bit Wide
CAM w/o LEs - 1 M4K RAM Block Can Emulate 32-Word 7-Bit Wide
CAM w/o LEs - Several M512/M4K Blocks Can Emulate Deeper
Wider CAMs - Flexibility Numbers of M512/M4K in Stratix
Makes This Scheme A Realistic One - Possible Implementation w/ MegaRAM Block
- Perform Sequential Search Through Memory At
Maximum Speed - Use MegaRAM Block Wide Data Bus Configurations To
Perform Several Comparisons Per Clock Cycle - Customers Specific CAM Requirements Must Be Well
Understood
23Appendix - 32-Word 7-Bit Wide CAM Design Files
Simulations Results
24VHDL Source Code Quartus II Archive
- library ieee
- use ieee.std_logic_1164.all
- entity MyCAM32Word7BitWide is
- port(
- -- Write Ports
- wrdata in std_logic_vector(6 downto 0)
- wraddress in std_logic_vector(4 downto 0)
- wrdelete_n in std_logic
- wren in std_logic
- wrclock in std_logic
- -- Match Ports
- matchdata in std_logic_vector(6 downto 0)
- syncmatchaddr out std_logic_vector(31 downto
0) - matchen in std_logic
- matchclock in std_logic)
- end
- architecture str of MyCAM32Word7BitWide is
signal matchaddress std_logic_vector(31 downto
0) signal data std_logic_vector(0 downto
0) signal address std_logic_vector(11 downto
0) begin data(0) lt wrdelete_n address lt
wrdata wraddress MyRAM_iMyRAM port
map ( data gt data, wren gt wren, wraddress
gt address, rdaddress gt matchdata, rden gt
matchen, wrclock gt wrclock, rdclock gt
matchclock, q gt matchaddress) -- Dummy
Process To Handle MatchAddress Results from
CAM process(matchclock) begin if
rising_edge(matchclock) then syncmatchaddr lt
matchaddress end if end process end
25Simulation Waveforms
- Operations Explanations
- Dont Write 0x00 _at_ 0x00
- Write 0x11 _at_ 0x01
- Dont Write 0x05 _at_ 0x05
- Write 0x22 _at_ 0x02
- Write 0x33 _at_ 0x03
- Write 0x11 _at_ 0x11 (Same Data Written At Two
Different Locations) - Match Data 0x00 gt Nothing Found
- Match Data 0x11 gt CAM Returns 0x20002 (Data
Found At Locations 0x01 0x11) - Match Data 0x05 gt Nothing Found
- Match Data 0x33 gt CAM Returns 0x8 (Data Found At
Location 0x03) - Delete Data 0x11 _at_ 0x01