XFT Review

1
XFT Review

• XFT Stereo Finder
• Design Review
• (FNAL)
• T. Shaw
• S. Holm

2
Finder Algorithm

• Finder Algorithm
• Similar to axial XFT
• 6 time bins(72 bits) vs 2 time bins(24 bits) per
  cell
• 8 cells vs 4 cells per FPGA
• 16.5ns clock vs 33ns clock
• Much larger Mask set
• L2 Pulsar Data(96 bits output)
• Implement in newest ALTERA Stratix 2 FPGA

3
Finder Chip
4
Finder Chip

• Input Alignment block receives wire data from 3
  TDC modules via an optical link and Mezzanine
  Receiver module, data is stored in FIFO Blocks,
  when all three of the FIFOs have data the FIFOs
  output Aligned Data with respect to a 16.5ns
  clock.
• It takes 396ns for the 6 time bins(24 slices at
  16.5ns) of data to be accumulated in the Wire
  Storage register. Once the 6 time bins are all
  registered the wire data is then processed by the
  Multiplexer every 16.5ns.
• The Multiplexer processes 12 cells. Processing
  involves assigning the wire data from 12 cells to
  a group of 133 bits for each of the 8 core cells.
  A new group is selected every 16.5ns. Wire data
  at the Multiplexer input is stable for 396ns(same
  time that the Storage register is gathering the
  next 24 slices of wire data).
• The MASK sets assign the 133 bits to particular
  nodes, counts the number of misses in a group of
  those twelve nodes and sets a Pbit if the number
  of misses is less than 3(or 2 or 1). A large
  number of Pbits are than OR'd together to
  sparsify the data down to 12 pixels or 96 pixels
  depending where the data is going.
• The MASK set processes 8 core cells worth of
  Information, a core cells pixels are output every
  16.5ns. It will take 132ns to process the 8 cells
  within a MASK. So there is 396ns-132ns264ns of
  dead time once the cells are processed.

5
Pixel Driver Chip
6
Pixel Driver Chip

• Pixel data from a group of 3 Finder chips(18 core
  cells) are accumulated in a FIFO within the Pixel
  Driver Chip. Two paths are used to send 18 cells
  worth of information to SLAM boards. The order
  of pixel cell data is shown on page 13 of the
  Finder Specification. Pixel Data from Finder C is
  split between the two paths.
• Once the first of the 8 time slices of pixel data
  arrives at the FIFOS the controller starts
  processing the data and sending it out to the
  Multiplexer. It will take 132ns(8 16.5ns) to get
  the data into the FIFOS and 297ns(18 16.5ns) to
  get it out.
• Total number of clock ticks from the time the
  first of 6 bins of wire data arrives at the
  Finder Chip until the 18th Cells Pixel Data is
  sent to the Mezzanine board and then onto the
  SLAM board is 53(53 16.5ns 874.5ns).

7
L2 Pulsar Chip
8
L2 Pulsar Chip

• 32 bits of Pixel data is stored as a slice in the
  FIFOs, 3 slices per Cell, 8 Cells from each
  Finder. The FIFO depth will be programmable so
  that on a L1 Accept the data will be output to
  the multiplexers and sent to the PULSAR board. If
  a L1 Accept isn't issued the FIFO slice is
  overwritten.
• Sending 96 bits per cell will require 3.564us to
  get the Information to the Pulsar board for the
  SL7 Board.
• 96 bits 8 cells per Finder Chip 4.5 Finder
  Chips 3,456 bits per Finder SL7 board, other
  layers will be less.
• The Mezzanine board that sends the information to
  the Pulsar board sends 16 bits every 16.5ns, so
  it will take gt
• 3,456/16 16.5ns 3.564us

9
Progress

• Finder Chip Design has been compiled simulated
  with 2 identical latest mask sets that process
  8 cells at the 16.5ns rate. (0 setup/hold time
  errors) (8.25ns rate had setup/hold time errors)
• Compilation Report
• Fitter Status Successful
  - Wed Oct 13 172400 2004
• Quartus II Version 4.1 Build 181
  06/29/2004 SJ Full Version
• Revision Name top_level
  
• Top-level Entity Name top_level
  
• Family Stratix II
  FLEX10K(SL3)
• Device
  EP2S60F484C3
  EPF10K50RC240-3
• Timing Models Preliminary
  
• Total ALUTs 10,602 /
  48,352 ( 21 ) vs 2,500/2,880 LE in
  XFT1
• Total pins 150 / 335
  ( 44 )
• Total memory bits 33,088 / 2,544,192
  ( 1 ) vs 6,912 / 40,960 in XFT1
• DSP block 9-bit elements 0 / 288 ( 0 )
  
• Total PLLs 0 / 6 ( 0 )
  
• Total DLLs 0 / 2 ( 0 )
  

10
Future

• Finder Chip Add L2 Pulsar data Mask and output.
  
• Pixel Driver Chip Implement in Software,
  Compile and Simulate.
• L2 Pulsar Chip - Implement in Software, Compile
  and Simulate.
• Develop Diagnostic Programs similar to XFT1 for
  all 3 Chips.
• http//www-ppd.fnal.gov/tshaw.myweb/Stereo_Finder.
  html